AD9523(RevC) Просмотр технического описания (PDF) - Analog Devices

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Компоненты Описание

производитель

AD9523
(Rev.:RevC)

Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs

Analog Devices 

Data Sheet

AD9523

Parameter

SCL, SDA Fall Time, tFALL

Data Setup Time, tSET; DAT

Data Hold Time, tHLD; DAT

Capacitive Load for Each Bus Line, CB1

Min

Typ Max

20 + 0.1 CB1

300

100

100

880

400

Unit Test Conditions/Comments

ns

ns

ns

This is a minor deviation from the original I²C

specification of 0 ns minimum2

pF

1 CB is the capacitance of one bus line in picofarads (pF).

2 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL

falling edge.

Rev. C | Page 11 of 60

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