AD9523(RevC) Просмотр технического описания (PDF) - Analog Devices
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производитель
AD9523
(Rev.:RevC)
(Rev.:RevC)
Analog Devices
AD9523 Datasheet PDF : 60 Pages
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AD9523
Data Sheet
Parameter
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup, tS
CS to SCLK Setup and Hold, tS, tC
CS Minimum Pulse Width High, tPWH
Min
Typ Max
Unit Test Conditions/Comments
1
µA
1
µA
2
pF
2.7
V
0.4
V
25
MHz
8
ns
12
ns
3.3
ns
0
ns
14
ns
10
ns
0
ns
6
ns
SERIAL CONTROL PORT—I²C MODE
VDD = VDD3_REF, unless otherwise noted.
Table 16.
Parameter
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
0.1 × VDD and 0.9 × VDD
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, tSPIKE
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIHMIN to VILMAX with
a Bus Capacitance from 10 pF to 400 pF
TIMING
Min
Typ
0.7 × VDD
−10
0.015 × VDD
20 + 0.1 CB1
Max
Unit
V
0.3 × VDD V
+10
µA
V
50
ns
0.4
V
250
ns
Clock Rate (SCL, fI2C)
Bus Free Time Between a Stop and Start
1.3
Condition, tIDLE
Setup Time for a Repeated Start Condition, tSET; 0.6
STR
Hold Time (Repeated) Start Condition, tHLD; STR 0.6
400
kHz
µs
µs
µs
Setup Time for Stop Condition, tSET; STP
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
SCL, SDA Rise Time, tRISE
0.6
1.3
0.6
20 + 0.1 CB1
µs
µs
µs
300
ns
Test Conditions/Comments
Note that all I2C timing values are referred to
VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD)
After this period, the first clock pulse is
generated
Rev. C | Page 10 of 60
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