AD9446 Просмотр технического описания (PDF) - Analog Devices
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AD9446 Datasheet PDF : 36 Pages
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AD9446
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Input Resistance
Input Capacitance
AD9446BSVZ-80
AD9446BSVZ-100
Temp Min Typ Max Min Typ Max Unit
Full
2.0
2.0
V
Full
0.8
0.8
V
Full
200
200 μA
Full
−10
+10 −10
+10 μA
Full
2
2
pF
Full
3.25
Full
3.25
0.2
V
0.2
V
Full
247
Full
1.125
545 247
1.375 1.125
545 mV
1.375 V
Full
0.2
0.2
V
Full
1.3
1.5 1.6
1.3
1.5 1.6
V
Full
1.1
1.4 1.7
1.1
1.4 1.7
kΩ
Full
2
2
pF
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1 (tCLKH)
CLK Pulse Width Low1 (tCLKL)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+)
Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9446BSVZ-80
Min Typ Max
80
1
12.5
5.0
5.0
3.35
2.1 3.6 4.8
13
60
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
AD9446BSVZ-100
Min Typ Max
100
1
10
4.0
4.0
3.35
2.3 3.6 4.8
13
60
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
ns
fsec
rms
Rev. 0 | Page 6 of 36
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