AD9446 Просмотр технического описания (PDF) - Analog Devices
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AD9446 Datasheet PDF : 36 Pages
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AD9446
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
Mnemonic Description
1
DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable
DCS (recommended); DCS = high (AVDD1) to disable DCS.
2
DNC
Do Not Connect. These pins should float.
3
OUTPUT CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
MODE
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4
DFS
Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS =
high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
5
LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, 38, AVDD1
43 to 45, 92 to 97
3.3 V (±5%) Analog Supply.
7
SENSE
Reference Mode Selection. Connect to AGND for internal 1.6 V reference (3.2 V p-p analog
input range); connect to AVDD1 for external reference.
8
VREF
1.6 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
9, 21, 24, 39, 42, 46, 91, 98, AGND
99, 100, Exposed Heat Sink
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
10
REFT
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB (Pin 11)
with 0.1 μF and 10 μF capacitors.
11
REFB
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 10) with 0.1 μF and 10 μF capacitors.
12 to 17, 25 to 31, 35, 37 AVDD2
5.0 V Analog Supply (±5%).
22
VIN+
Analog Input—True.
23
VIN−
Analog Input—Complement.
40
CLK+
Clock Input—True.
41
CLK−
Clock Input—Complement.
47, 63, 75, 87,
DRGND
Digital Output Ground.
48, 64, 76, 88
DRVDD
3.3 V Digital Output Supply (3.0 V to 3.6 V).
49
D0− (LSB) D0 Complement Output Bit (LVDS Levels).
50
D0+
D0 True Output Bit.
51
D1−
D1 Complement Output Bit.
52
D1+
D1 True Output Bit.
53
D2−
D2 Complement Output Bit.
54
D2+
D2 True Output Bit.
55
D3−
D3 Complement Output Bit.
56
D3+
D3 True Output Bit.
57
D4−
D4 Complement Output Bit.
58
D4+
D4 True Output Bit.
59
D5−
D5 Complement Output Bit.
60
D5+
D5 True Output Bit.
61
D6−
D6 Complement Output Bit.
62
D6+
D6 True Output Bit.
65
D7−
D7 Complement Output Bit.
66
D7+
D7 True Output Bit.
67
DCO−
Data Clock Output—Complement.
68
DCO+
Data Clock Output—True.
69
D8−
D8 Complement Output Bit.
70
D8+
D8 True Output Bit.
71
D9−
D9 Complement Output Bit.
72
D9+
D9 True Output Bit.
73
D10−
D10 Complement Output Bit.
74
D10+
D10 True Output Bit.
77
D11−
D11 Complement Output Bit.
78
D11+
D11 True Output Bit.
Rev. 0 | Page 11 of 36
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