AD9388ABSTZ-A5 Просмотр технического описания (PDF) - Analog Devices

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AD9388ABSTZ-A5

10-Bit Integrated, Multiformat, HDTV Video Decoder, RGB Graphics Digitizer, and 2:1 Multiplexed HDMI/DVI Interface

Analog Devices 

Pin No.

24 to 33, 36 to 47, 52 to 55,

58 to 61

19

Mnemonic

P0 to P29

INT1

20

SYNC_OUT/INT2

17

HS/CS

18

VS/FIELD

16

DE/FIELD

11

SDA

12

SCL

13

ALSB

21

RESET

51

LLC

65

XTAL1

66

XTAL

70

ELPF

102

AUDIO_ELPF

85

REFOUT

86

CML

90

REFN

92

REFP

63

HS_IN/CS_IN

62

VS_IN

75

SOG

97

SOY

112

RXA_CN

113

RXA_CP

115

RXA_0N

116

RXA_0P

118

RXA_1N

119

RXA_1P

AD9388A

Type1 Description

O

Video Pixel Output Port.

O

Interrupt. Can be active low or active high. The set of events that

triggers an interrupt is under user control.

O

Sliced Synchronization Output Signal (SYNC_OUT).

Interrupt Signal (INT2).

O

Horizontal Synchronization Output Signal (HS).

Composite Synchronization (CS). A single signal containing both

horizontal and vertical synchronization pulses.

O

Vertical Synchronization Output Signal (VS).

Field Synchronization (FIELD). Field synchronization output signal in

all interlaced video modes.

O

Data Enable Signal (DE). Indicates active pixel data.

Field Synchronization (FIELD). Field synchronization output signal in

all interlaced video modes.

I/O

I2C Port Serial Data Input/Output Pin. SDA is the data line for the

control port.

I

I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is

the clock line for the control port.

I

This pin sets the second LSB of each AD9388A register map.

I

System Reset Input. Active low. A minimum low reset pulse width of

5 ms is required to reset the AD9388A circuitry.

O

Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz.

O

This pin should be connected to the 28.63636 MHz crystal or left as a

no connect if an external 3.3 V 28.63636 MHz clock oscillator source is

used to clock the AD9388A. In crystal mode, the crystal must be a

fundamental crystal.

I

Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by

an external 3.3 V 28.63636 MHz clock oscillator source to clock the

AD9388A.

O

The recommended external loop filter must be connected to this

ELPF pin.

O

The recommended external loop filter must be connected to this

AUDIO_ELPF pin.

O

Internal Voltage Reference Output.

O

Common-Mode Level for the Internal ADCs.

I

Internal Voltage Output.

I

Internal Voltage Output.

I

HS Input Signal. Used in analog mode for 5-wire timing mode.

CS Input Signal. Used in analog mode for 4-wire timing mode.

For optimal performance, a 100 Ω series resistor is recommended on

the HS_IN/CS_IN pin.

I

VS Input Signal. This pin is used in analog mode for 5-wire timing

mode. For optimal performance, a 100 Ω series resistor is

recommended on the VS_IN pin.

I

Synchronization-on-Green Input. This pin is used in embedded

synchronization mode.

I

Synchronization-on-Luma Input. This pin is used in embedded

synchronization mode.

I

Digital Input Clock Complement of Port A in the HDMI Interface.

I

Digital Input Clock True of Port A in the HDMI Interface.

I

Digital Input Channel 0 Complement of Port A in the HDMI Interface.

I

Digital Input Channel 0 True of Port A in the HDMI Interface.

I

Digital Input Channel 1 Complement of Port A in the HDMI Interface.

I

Digital Input Channel 1 True of Port A in the HDMI Interface.

Rev. B | Page 11 of 28

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