AD9267 Просмотр технического описания (PDF) - Analog Devices

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AD9267

10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator

Analog Devices 

AD9267

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK– 1

CVDD 2

PDWNA 3

PDWNB 4

PLL_LOCKED 5

DVDD 6

DGND 7

DRVDD 8

D0–B 9

D0+B 10

D1–B 11

D1+B 12

D2–B 13

D2+B 14

D3–B 15

D3+B 16

PIN 1

INDICATOR

AD9267

TOP VIEW

(Not to Scale)

48 SCLK/PLLMULT0

47 SDIO/PLLMULT1

46 PLLMULT2

45 PLLMULT3

44 PLLMULT4

43 DVDD

42 DGND

41 DRVDD

40 D3+A

39 D3–A

38 D2+A

37 D2–A

36 D1+A

35 D1–A

34 D0+A

33 D0–A

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE

LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB

INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING

THE THERMAL CAPACITY OF THE PACKAGE.

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

1

CLK−

2

CVDD

3, 4

PDWNA, PDWNB

5

PLL_LOCKED

6, 25, 43

DVDD

7, 24, 42

DGND

8, 23, 41

DRVDD

9 to 16

D0−B, D0+B to D3−B, D3+B

17, 18

OR−B, OR+B

19, 20

DCO−, DCO+

21, 22, 26 to 30 DNC

31, 32

OR−A, OR+A

33 to 40

D0−A, D0+A to D3−A, D3+A

44, 45, 46

PLLMULT4, PLLMULT3, PLLMULT2

47

SDIO/PLLMULT1

48

SCLK/PLLMULT0

49

CSB

50

RESET

51, 62

AGND

52, 55, 58, 61 AVDD

53, 54

VIN+A, VIN−A

56

VREF

57

CFILT

59, 60

VIN+B, VIN−B

63

CGND

64

CLK+

65

Exposed paddle (EPAD)

Description

Differential Clock Input (−).

Clock Supply (1.8 V).

Power-Down Pins. Active high.

PLL Lock Indicator.

Digital Supply (1.8 V).

Digital Ground.

Digital Output Driver Supply

Channel B Differential LVDS Data Output Bits. D0+B is the LSB and D3+B is the MSB.

Channel B Overrange Indicator Pins.

Differential Data Clock Output.

Do Not Connect.

Channel A Overrange Indicator Pins.

Channel A Differential LVDS Data Output Bits. D0+A is the LSB and D3+A is the MSB.

PLL Mode Selection Pins.

Serial Port Interface Data Input/Output/PLL Mode Selection Pins.

Serial Port Interface Clock/PLL Mode Selection Pins.

Serial Port Interface Chip Select Pin Active Low.

Chip Reset.

Analog Ground.

Analog Supply (1.8 V).

Channel A Analog Input.

Voltage Reference Input.

Noise Limiting Filter Capacitor.

Channel B Analog Input.

Clock Ground.

Differential Clock Input (+).

Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The

exposed paddle must be soldered to analog ground of the PCB to achieve optimal electrical

and thermal performance.

Rev. 0 | Page 8 of 24

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