AD9265 Просмотр технического описания (PDF) - Analog Devices
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AD9265 Datasheet PDF : 44 Pages
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Data Sheet
AD9265
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Min
Typ
Max Unit
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
0.30
ns
0.40
ns
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an
10
ns
output relative to the SCLK falling edge
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
10
ns
input relative to the SCLK rising edge
Timing Diagrams
N–1
VIN
tA
N
N+1
N+2
N+3
N+4
N+5
CLK+
tCH
tCL
tCLK
CLK–
DCO/DCO+
tDCO
DCO–
LVDS (DDR) MODE
D0/1+ TO D14/D15+
D0/1– TO D14/D15–
tSKEW
tPD
DEx
DOx
DEx
DOx
DEx
DOx
DEx
DOx
DEx
DOx
– 12
– 12
– 11
– 11
– 10
– 10
–9
–9
–8
–8
CMOS MODE
D0 TO D15
Dx – 12
Dx – 11
Dx – 10
Dx – 9
Dx – 8
NOTES
1. DEx DENOTES EVEN BIT.
2. DOx DENOTES ODD BIT.
Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing
CLK+
SYNC
tSSYNC
tHSYNC
Figure 3. SYNC Input Timing Requirements
Rev. C | Page 9 of 44
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