AD9265 Просмотр технического описания (PDF) - Analog Devices
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AD9265 Datasheet PDF : 44 Pages
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AD9265
Data Sheet
Parameter1
WORST OTHER (HARMONIC OR SPUR)
Without Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
With On-Chip Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO-TONE SFDR
Without Dither
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
AD9265BCPZ-802
Min Typ Max
−106
−106
−97
−104
−102
−106
−106
−97
−104
−101
93
80
650
AD9265BCPZ-1052
Min Typ Max
−105
−104
−95
−103
−103
−105
−105
−99
−103
−101
90
78
650
AD9265BCPZ-1252
Min Typ Max Unit
−101
dBc
−103
dBc
−92 dBc
−104
dBc
−100
dBc
−102
dBc
−103
dBc
−98 dBc
−104
dBc
−100
dBc
95
dBc
79
dBc
650
MHz
1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 The suffix following the part number refers to the model found in the Ordering Guide section.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS
enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
CMOS/LVDS/LVPECL
0.9
0.3
3.6
AGND
AVDD
0.9
1.4
−100
+100
−100
+100
4
8
10
12
AGND
1.2
AGND
−100
−100
12
CMOS
0.9
1
16
AVDD
AVDD
0.6
+100
+100
20
Unit
V
V p-p
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
Rev. C | Page 6 of 44
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