AD9222 Просмотр технического описания (PDF) - Analog Devices
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AD9222 Datasheet PDF : 61 Pages
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Data Sheet
AD9222
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter 1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x),
(ANSI-644)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal
Option)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
AD9222-40
Min Typ Max
AD9222-50
Min Typ Max
AD9222-65
Min Typ Max
Unit
CMOS/LVDS/LVPECL
250
1.2
20
1.5
CMOS/LVDS/LVPECL
250
1.2
20
1.5
CMOS/LVDS/LVPECL
250
1.2
20
1.5
mV p-p
V
kΩ
pF
1.2
3.6
0
0.3
30
0.5
1.2
3.6
0.3
30
0.5
1.2
3.6
V
0.3
V
30
kΩ
0.5
pF
1.2
3.6
0
0.3
70
0.5
1.2
3.6
0.3
70
0.5
1.2
3.6
V
0.3
V
70
kΩ
0.5
pF
1.2
DRVDD + 0.3 1.2
DRVDD + 0.3 1.2
DRVDD + 0.3 V
0
0.3
0
0.3
0
0.3
V
30
30
30
kΩ
2
2
2
pF
1.79
0.05
1.79
0.05
1.79
V
0.05
V
247
1.125
LVDS
454
1.375
Offset binary
247
1.125
LVDS
454
1.375
Offset binary
LVDS
247
454
mV
1.125
1.375
V
Offset binary
LVDS
150
250
1.10
1.30
Offset binary
LVDS
150
250
1.10
1.30
Offset binary
LVDS
150
250
mV
1.10
1.30
V
Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO pins sharing the same connection.
Rev. F | Page 5 of 60
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