AD9101SE Просмотр технического описания (PDF) - Analog Devices

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AD9101SE

125 MSPS Monolithic Sampling Amplifier

Analog Devices 

AD9101

Acquisition Time is the amount of time it takes the AD9101

to reacquire the analog input when switching from hold to track

mode. The interval starts at the 50% clock transition point and

ends when the input signal is reacquired to within a specified

error band at the hold capacitor.

Aperture Delay establishes when the input signal is actually

sampled. It is the time difference between the analog propaga-

tion delay of the front-end buffer and the control switch delay

time (the time from the hold command transition to when the

switch is opened). For the AD9101, this is a negative value,

meaning that the analog delay is longer than the switch delay.

Aperture Jitter is the random variation in the aperture delay.

This is measured in ps-rms and is manifested as phase noise on

the held signal.

Droop Rate is the change in output voltage as a function of

time (dV/dt). It is measured at the AD9101 output with the de-

vice in hold mode and the input held at a specified dc value; the

measurement starts immediately after the T/H switches from

track to hold.

Feedthrough Rejection is the ratio of the output signal to the

input signal when in hold mode. This is a measure of how well

the switch isolates the input signal from feeding through to the

output.

Hold-to-Track Switch Delay is the time delay from the track

command to the point when the output starts to change to ac-

quire a new signal level.

Pedestal Offset is the offset voltage measured immediately af-

ter the AD9101 is switched from track to hold with the input

held at zero volts. It manifests itself as a dc offset during the

hold time.

Sampling Bandwidth is the –3 dB frequency response from

the input to the hold capacitor under sampling conditions. It is

greater than the tracking bandwidth because it does not include

the bandwidth of the output amplifier which is optimized for

settling time rather than bandwidth.

Track-to-Hold Settling Time is the time necessary for the

track to hold switching transient to settle to within 4 mV of its

final value.

Track-to-Hold Switching Transient is the maximum peak

switch induced transient voltage which appears at the AD9101

output when it is switched from track to hold.

+2V

ANALOG

INPUT (x 4) 0V

-2V

+2V

HOLD TO TRACK

SWITCH DELAY

TIME (1.5 ns)

SAMPLER OUTPUT SIGNAL (x 4)

AND AMPLIFIER OUTPUT SIGNAL 0V

VOLTAGE

LEVEL HELD

ACQUISITION

TIME (SEE

TEXT)

OBSERVED AT

HOLD CAPACITOR

OBSERVED AT

AMPLIFIER OUTPUT

-2V

"1"

CLOCK

INPUTS

"0"

CLOCK

"HOLD"

CLOCK

"TRACK"

Timing Diagram (500 ps/div)

APERTURE

DELAY

(–0.25 ns)

TRACK TO

HOLD

SETTLING

(4 ns)

CLOCK

"HOLD"

–4–

REV. 0

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