AD9022SQ Просмотр технического описания (PDF) - Analog Devices

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AD9022SQ

12-Bit 20 MSPS Monolithic A/D Converter

Analog Devices 

AD9022

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track-and-hold (T/H). The T/H holds whatever analog value is

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AIN = 1.2MHz

present when the unit is strobed with an ENCODE command.

AIN = –1.0dBFS

The conversion process begins on the rising edge of this pulse,

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SNR = 66.7dB

THD = 77.51dB

which should conform to the minimum and maximum pulse

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SFDR = 79.49dBFS

width requirements shown in the specifications. Operation be-

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low the recommended encode rate (4 Msps) may result in ex-

cessive droop in the internal T/H devices–leading to large dc

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and ac errors.

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The held analog value of the first track-and-hold is applied to a

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5-bit flash converter and a second T/H. The 5-bit flash con-

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verter resolves the most significant bits (MSBs) of the held ana-

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FREQUENCY – MHz

log voltage. These 5 bits are reconstructed via a 5-bit DAC and

subtracted from the original T/H output signal to form a residue

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signal.

A second T/H holds the amplified residue signal while it is en-

OBSOLETE Figure8. FFTPlot

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AIN = 9.6MHz

AIN = –1.0dBFS

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SNR = 66.05dB

THD = 74.28dB

SFDR = 75.32dBFS

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FREQUENCY – MHz

coded with a second 5-bit flash ADC. Again the 5 bits are re-

constructed and subtracted from the second T/H output to form

a residue signal. This residue is amplified and encoded with a 4-

bit flash ADC to provide the 3 least significant bits (LSBs) of

the digital output and one bit of error correction.

Digital Error Correction logic aligns the data from the three

flash converters and presents the result as a 12-bit parallel digi-

tal word. The output stage of the AD9022 is TTL. Output data

may be strobed on the rising edge of the ENCODE command.

AD9022 IN RECEIVER APPLICATIONS

Advances in semiconductor processes have resulted in low cost

digital signal processing (DSP) and analog signal processing

which can help create cost effective alternative receiver designs.

Today, an all-digital receiver allows tuning, demodulation, and

detection of receiver signals in the digital domain. By digitizing

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IF signals directly and utilizing digital techniques, it becomes

possible to make significant improvements in receiver design.

Figure 9. FFT Plot

For high frequency IFs, the ADC is the key to the receiver’s per-

formance. Unfortunately, the specifications frequently used by

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receiver designers and analog-to-digital (ADC) manufacturers

AIN1 = 8.9MHz

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AIN2 = 9.8MHz

AIN1 = 7.0dBFS

AIN2 = 7.0dBFS

SFDR = 80.62dBFS

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are often very different. Noise Figure and Intercept Point are

common measures of noise and linearity in analog RF system

design. ADCs are more frequently specified in terms of SNR

and harmonic distortion.

Noise

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Noise figure (NF) is a measure of receiver sensitivity and is de-

fined as the degradation of signal-to-noise ratio (SNR) as a sig-

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nal passes through a device. In equation form:

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4.0

6.0

8.0

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FREQUENCY – MHz

NF = SNR (in) – SNR (out)

Noise figure is a bandwidth invariant parameter for reasonably

narrow bandwidths in most devices. The system noise figure for

a combination of amplifiers and mixers, for instance, can be

analyzed without regard to the information bandwidth.

Figure 10. Two Tone FFT

THEORY OF OPERATION

Refer to the block diagram.

Thermal noise contribution from the ADC behaves in a similar

fashion; however, the spectral density of quantization noise is a

function of the sample rate. In addition, the spectral density of

the quantization noise is flat only in an ADC with perfect linear-

ity, i.e., perfect 1 LSB step sizes.

The AD9022 employs a three-pass subranging architecture and

digital error correction. This combination of design techniques

ensures 12-bit accuracy at relatively low power.

Analog input signals are immediately attenuated through a resis-

tor divider and applied directly to the sampling bridge of the

To analyze the system noise performance, ADC noise figure is

calculated by normalizing the SNR of the ADC output to a 1

Hz bandwidth. This result is given by:

SNR (/Hz) = SNR + 10 log10 (Fs/2)

where Fs is the sample rate.

REV. A

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