AD8324(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD8324 Datasheet PDF : 16 Pages
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FEATURES
Supports DOCSIS 2.0 and Euro-DOCSIS standards for
reverse path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 61 dBmV output:
–59 dBc SFDR at 21 MHz
–54 dBc SFDR at 65 MHz
Output noise level @ minimum gain 1.3 nV/√Hz
Maintains 75 Ω output impedance in TX-enable and
Transmit-disable condition
Upper bandwidth: 100 MHz (full gain range)
3.3 V supply operation
Supports SPI® interfaces
APPLICATIONS
DOCSIS 2.0 and Euro-DOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
GENERAL DESCRIPTION
The AD83241 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8324
ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications.
The gain of the AD8324 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8324 accepts a differential or single-ended input signal.
The output is specified for driving a 75 Ω load through a 1:1
transformer.
Distortion performance of –54 dBc is achieved with an output
level up to 61 dBmV at 65 MHz bandwidth.
This device has a sleep mode function that reduces the quies-
cent current to 30 µA and a full power-down function that
reduces power-down current to 2.5 mA.
The AD8324 is packaged in a low cost 20-lead LFCSP package
and a 20-lead QSOP package. The AD8324 operates from a
single 3.3 V supply.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
3.3 V Upstream
Cable Line Driver
AD8324
FUNCTIONAL BLOCK DIAGRAM
BYP
VIN+
VIN–
DIFF
OR SINGLE
INPUT
AMP
VERNIER
ZIN (SINGLE) = 550Ω
ZIN (DIFF) = 1100Ω
AD8324
VOUT+
ATTENUATION
CORE
8
OUTPUT
STAGE
ZOUT DIFF =
75Ω
VOUT–
DECODE
8
DATA LATCH
POWER-
DOWN LOGIC
RAMP
8
SHIFT
REGISTER
GND DATEN DATA CLK
TXEN SLEEP
Figure 1. Functional Block Diagram
–40
–50
VOUT = 61dBmV @ DEC 60
THIRD HARMONIC
–60
–70
VOUT = 61dBmV @ DEC 60
SECOND HARMONIC
–80
5
15
25
35
45
55
65
FREQUENCY (MHz)
Figure 2. Worst Harmonic Distortion vs. Frequency
1 Patent pending.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
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