AD824AR-16 Просмотр технического описания (PDF) - Analog Devices
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AD824AR-16 Datasheet PDF : 16 Pages
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AD824
WAFER TEST LIMITS (@ VS = +5.0 V, VCM = 0 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
Supply Current/Amplifier
VOS
IB
IOS
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
VCM = 0 V to 2 V
V = + 2.7 V to +12 V
RL = 2 kΩ
ISOURCE = 20 µA
ISINK = 20 µA
VO = 0 V, RL = ∞
1.0
12
20
–0.2 to 3.0
66
70
15
4.975
25
600
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly
methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice
lot qualifications through sample lot assembly and testing.
DICE CHARACTERISTICS
mV max
pA max
pA
V min
dB min
µV/V
V/mV min
V min
mV max
µA max
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS – 0.2 V to +VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD824A, B . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
θJA2
θJC
Units
AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils.
Substrate (Die Backside) Is Connected to V+. Transistor
Count, 143.
14-Pin Plastic DIP (N)
76
33
°C/W
14-Pin SOIC (R)
120
36
°C/W
16-Pin SOIC (R)
92
27
°C/W
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts unless
otherwise noted.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC
package.
Model
ORDERING GUIDE
Temperature
Range
Package Option
AD824AN
AD824BN
AD824AR
AD824AR-3V
AD824AN-3V
AD824AR-14
AD824AR-14-3V
AD824AR-16
AD824AChips
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
+25°C
14-Pin Plastic DIP
14-Pin Plastic DIP
14-Pin SOIC
14-Pin SOIC
14-Pin Plastic DIP
14-Pin SOIC
14-Pin SOIC
16-Pin SOIC
DICE
VCC
R1
R2
I5
I6
Q18 Q29
R9
Q21 Q27
Q4
Q6
C3
+IN J1
J2
Q5
Q19
Q20
Q7
R7
R13
R15
–IN
C2
Q22
Q23
C4
VOUT
Q24 Q25
Q8
C1
Q2
Q3
R12
R14
I1
I2
I3
I4
Q31
Q28
Q26
R17
VEE
CAUTION
Figure 1. Simplified Schematic of 1/4 AD824
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD824 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. A
–5–
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