EVAL-AD7898CB Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
EVAL-AD7898CB Datasheet PDF : 16 Pages
| |||
AD7898
TIMING SPECIFICATIONS1 (VDD = 4.75 V to 5.25 V; VDRIVE = 2.7 V to 5.25 V; REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise
noted.)
Parameter
Limit at TMIN, TMAX Unit
Description
Mode 0 Operation
t1
40
t2
262
t3
262
302
302
t4
603
t4
703
t5
20
t6
504
tCONVERT
3.3
Mode 1 Operation
fSCLK5
1
3.7
tCONVERT
16 × tSCLK
4.33
tQUIET
100
t2
70
t33
40
t43
80
t5
108
t6
108
t7
60
t84
20
60
tPOWER-UP
4.33
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
µs
CONVST Pulse Width
SCLK High Pulse Width, VDRIVE = 5 V ± 5%
SCLK Low Pulse Width, VDRIVE = 5 V ± 5%
SCLK High Pulse Width VDRIVE = 2.7 V to 3.6 V
SCLK Low Pulse Width VDRIVE = 2.7 V to 3.6 V
Data Access Time after Falling Edge of SCLK, VDRIVE = 5 V ± 5%
Data Access Time after Falling Edge of SCLK, VDRIVE = 2.7 V to 3.6 V
Data Hold Time after Falling Edge of SCLK
Bus Relinquish Time after Falling Edge of SCLK
kHz min
MHz max
µs max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
tSCLK = 1/fSCLK
fSCLK = 3.7 MHz
Minimum Quiet Time Required between Conversions
CS to SCLK Setup Time
Delay from CS Until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Power-Down Mode
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
2The SCLK maximum frequency is 15 MHz for Mode 0 operation for 220 kSPS throughput with V DRIVE = 5 V ± 5%, SCLK = 13 MHz with VDRIVE = 2.7 V to 3.6 V.
The mark/space ratio for SCLK is specified for at least 40% high time (with corresponding 60% low time) or 40% low time (with corresponding 60% high time). As
the SCLK frequency is reduced, the mark/space ratio may vary, provided limits are not exceeded. Care must be taken when interfacing to account for the data access
time, t4, and the set-up time required for the users processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with.
See Serial Interface section.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t6 and t8 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6 and t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
5Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Specifications subject to change without notice.
REV. A
–3–
Share Link: 