EVAL-AD7888CB(1999) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
EVAL-AD7888CB
(Rev.:1999)
(Rev.:1999)
Analog Devices
EVAL-AD7888CB Datasheet PDF : 16 Pages
| |||
AD7888
Figure 4 shows the typical power supply rejection ratio vs.
frequency for the part. The power supply rejection ratio is de-
fined as the ratio of the power in the ADC output at frequency f
to the power of a full-scale sine wave applied to the ADC of
frequency fS:
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fs in ADC full scale input. Here a 100 mV peak-to-peak
sine wave is coupled onto the VDD supply. Both the +2.7 V and
+5.5 V supply performances are shown.
–75
–77 VDD = +5.5V/+2.7V
100mV p-p SINE WAVE ON VDD
–79 REFIN = 2.488V EXT REFERENCE
–81
–83
–85
–87
–89
–91
–93
2.65
12.85
23.15 33.65 43.85
INPUT FREQUENCY – kHz
54.35
Figure 4. PSRR vs. Frequency
64.15
CIRCUIT INFORMATION
The AD7888 is a fast, low power, 12-bit, single supply, 8-
channel A/D converter. The part can be operated from +3 V
(+2.7 V to +3.6 V) supply or from +5 V (+4.75 V to +5.25 V)
supply. When operated from either a +5 V supply or a +3 V
supply, the AD7888 is capable of throughput rates of 125 kSPS
when provided with a 2 MHz clock.
The AD7888 provides the user with an 8-channel multiplexer,
on-chip track/hold, A/D converter, reference and serial interface
housed in a tiny 16-lead TSSOP package, which offers the user
considerable space saving advantages over alternative solutions.
The serial clock input accesses data from the part and also
provides the clock source for the successive-approximation
A/D converter. The analog input range is 0 to VREF (where
the externally-applied VREF can be between +1.2 V and VDD).
The 8-channel multiplexer is controlled by the part’s Control
Register. This Control Register also allows the user to power-off
the internal reference and to determine the Modes of Operation.
CONVERTER OPERATION
The AD7888 is a successive-approximation analog-to-digital
converter based around a charge redistribution DAC. Figures 5
and 6 show simplified schematics of the ADC. Figure 5 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in Position A, the comparator is held in a balanced condition
and the sampling capacitor acquires the signal on AIN.
A
AIN
SAMPLING
CAPACITOR
SW1 B
AGND
ACQUISITION
PHASE
SW2
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
(REF IN/REF OUT)/2
Figure 5. ADC Acquisition Phase
When the ADC starts a conversion, (see Figure 6), SW2 will
open and SW1 will move to Position B causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 7 shows the ADC transfer
function.
A
VIN
SAMPLING
CAPACITOR
SW1
B CONVERSION
AGND
PHASE
CHARGE
REDISTRIBUTION
DAC
SW2 COMPARATOR
CONTROL
LOGIC
(REF IN/REF OUT)/2
Figure 6. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7888 is straight binary. The de-
signed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/4096. The
ideal transfer characteristic for the AD7888 is shown in Figure 7
below.
111...111
111...110
111...000
011...111
1LSB = VREF/4096
000...010
000...001
000...000
0.5LSB
0V
+VREF – 1.5LSB
ANALOG INPUT
Figure 7. Transfer Characteristic
–8–
REV. 0
Share Link: