EVAL-AD7888CB(1999) Просмотр технического описания (PDF) - Analog Devices
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Компоненты Описание
производитель
EVAL-AD7888CB
(Rev.:1999)
(Rev.:1999)
Analog Devices
EVAL-AD7888CB Datasheet PDF : 16 Pages
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AD7888
TIMING SPECIFICATIONS1 (TA = TMIN to TMAX , unless otherwise noted)
Parameter
Limit at TMIN, TMAX
(A, B Versions)
+4.75 V to +5.25 V +2.7 V to +3.6 V Units
Description
fSCLK2
tCONVERT
tACQ
t1
t23
t33
t4
t5
t6
t7
t84
t9
2
14.5 tSCLK
1.5 tSCLK
10
30
75
20
20
0.4 tSCLK
0.4 tSCLK
80
5
2
14.5 tSCLK
1.5 tSCLK
10
60
100
20
20
0.4 tSCLK
0.4 tSCLK
80
5
MHz max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs typ
Throughput Time = tCONVERT + tACQ = 16 tSCLK
CS to SCLK Setup Time
Delay from CS until DOUT 3-State Disabled
Data Access Time after SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to DOUT High Impedance
Power-Up Time from Shutdown
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V ± 10% and time for an output to
cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.
4t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
IOL
TO
OUTPUT
PIN
CL
50pF
200A
IOH
+1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
–4–
REV. 0
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