AD7877ACBZ-REEL Просмотр технического описания (PDF) - Analog Devices
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AD7877ACBZ-REEL Datasheet PDF : 46 Pages
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Data Sheet
AD7877
TIMING SPECIFICATIONS
TA = TMIN to TMAX, unless otherwise noted, VCC = 2.7 V to 5.25 V, VREF = 2.5 V. Sample tested at 25°C to ensure compliance. All input
signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
fDCLK 1
t1
t2
t3
t4
t5
t6 2
t72
t8 3
t9
Limit at TMIN, TMAX
10
20
16
20
20
12
12
16
16
16
0
Unit
kHz min
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
Description
CS falling edge to first DCLK rising edge
DCLK high pulse width
DCLK low pulse width
DIN setup time
DIN hold time
CS falling edge to DOUT, three-state disabled
DCLK falling edge to DOUT valid
CS rising edge to DOUT high impedance
CS rising edge to DCLK ignored
1 Mark/space ratio for the DCLK input is 40/60 to 60/40.
2 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V.
3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
TIMING DIAGRAMS
CS
DCLK
DIN
DOUT
t1
1
MSB
t2
2
t4
t3
3
t5
t6
t7
MSB
t9
15
16
LSB
t8
LSB
Figure 2. Detailed Timing Diagram
200µA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 3. Load Circuit for Digital Output Timing Specifications
Rev. E | Page 5 of 45
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