AD7818ARMZ-REEL Просмотр технического описания (PDF) - Analog Devices
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AD7818ARMZ-REEL Datasheet PDF : 20 Pages
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AD7817/AD7818
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Sample tested during initial
release and after any redesign or process changes that may affect the parameters. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V. See Figure 17, Figure 18, Figure 21, and Figure 22.
Table 2.
Parameter
tPOWER-UP
t1a
t1b
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t121
t131
t14a1, 2
t14b1, 2
t15
t16
t17
A Version/B Version
2
9
27
20
50
0
0
10
10
40
40
0
0
20
20
30
30
150
40
400
Unit
µs max
µs max
µs max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
Test Conditions/Comments
Power-up time from rising edge of CONVST
Conversion time Channel 1 to Channel 4
Conversion time temperature sensor
CONVST pulse width
CONVST falling edge to BUSY rising edge
CS falling edge to RD/WR falling edge setup time
RD/WR falling edge to SCLK falling edge setup
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK low pulse width
SCLK high pulse width
CS falling edge to RD/WR rising edge setup time
RD/WR rising edge to SCLK falling edge setup time
DOUT access time after RD/WR rising edge
DOUT access time after SCLK falling edge
DOUT bus relinquish time after falling edge of RD/WR
DOUT bus relinquish time after rising edge of CS
BUSY falling edge to OTI falling edge
RD/WR rising edge to OTI rising edge
SCLK rising edge to CONVST falling edge (acquisition time of T/H)
1 These figures are measured with the load circuit of Figure 3. They are defined as the time required for DOUT to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and 0.4 V or 2 V for
VDD = 3 V ± 10%, as shown in Table 1.
2 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of the external bus loading capacitances.
200µA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200µA
IOL
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
Rev. D | Page 6 of 20
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