AD7801 Просмотр технического описания (PDF) - Analog Devices

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AD7801

+2.7 V to +5.5 V, Parallel Input,Voltage Output 8-Bit DAC

Analog Devices 

AD7801

Figure 27 shows a typical setup for the AD7801 when using its

internal reference. The internal reference is selected by tying the

REFIN pin to VDD. Internally in the reference section there is a

reference detect circuit that will select the internal VDD/2 based

on the voltage connected to the REFIN pin. If REFIN is within

a threshold voltage of a PMOS device (approximately 1 V) of

VDD the internal reference is selected. When the REFIN voltage

is more than 1 V below VDD, the externally applied voltage at

this pin is used as the reference for the DAC. The internal

reference on the AD7801 is VDD/2, the output current to

voltage converter within the AD7801 provides a gain of two.

Thus the output range of the DAC is from 0 V to VDD, based on

Table I.

VDD = 3V TO 5V

0.1␮F

10␮F

VDD AGND DGND

REF IN

CLR

AD7801

VOUT

VOUT

PD

D7-D0

CS WR LDAC

VDD

DATA BUS CONTROL

INPUTS

Figure 27. Typical Configuration Selecting the Internal

Reference

Figure 28 shows a typical setup for the AD7801 when using an

external reference. The reference range for the AD7801 is from

1 V to VDD/2 V. Higher values of reference can be incorporated

but will saturate the output at both the top and bottom end of

the transfer function. There is a gain of two from input to output

on the AD7801. Suitable references for 5 V operation are the

AD780 and REF192. For 3 V operation a suitable external

reference would be the AD589 a 1.23 V bandgap reference.

VDD = 3V TO 5V

0.1␮F 10␮F

VIN

EXT REF VOUT

GND

0.1␮F

AD780/REF192 WITH VDD = 5V

OR

AD589 WITH VDD = 3V

VDD

VDD AGND DGND

REF IN

CLR

AD7801 VOUT

PD

D7-D0

CS WR LDAC

VOUT

DATA BUS CONTROL

INPUTS

Figure 28. Typical Configuration Using An External

Reference

MICROPROCESSOR INTERFACING

AD7801–ADSP-2101/ADSP-2103 Interface

Figure 29 shows an interface between the AD7801 and the ADSP-

2101/ADSP-2103. The fast interface timing associated with the

AD7801 allows easy interface to the ADSP-2101/ADSP-2103.

LDAC is permanently tied low in this circuit so the DAC

output is updated on the rising edge of the WR signal.

Data is loaded to the AD7801 input register using the following

ADSP-21xx instruction.

DM(DAC) = MR0

MR0 = ADSP-21xx MR0 Register.

DAC = Decoded DAC Address.

DMA14

DMA0

ADDRESS BUS

DMS

ADSP-2101*/

ADSP-2103*

WR

EN ADDR

DECODE

AD7801*

CS

LDAC

WR

DB7

DB0

DMD15

DMD0

DATA BUS

*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.

Figure 29. AD7801–ADSP-2101/ADSP-2103 Interface

AD7801–TMS320C20 Interface

Figure 30 shows an interface between the AD7801 and the

TMS320C20. Data is loaded to the AD7801 using the following

instruction:

OUT DAC, D

DAC = Decoded DAC Address.

D = Data Memory Address.

A15

ADDRESS BUS

A0

IS

TMS320C20

STRB

R/W

EN ADDR

DECODE

AD7801*

CS

LDAC

WR

DB7

DB0

D15

DATA BUS

D0

*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.

Figure 30. AD7801–TMS320C20 Interface

–10–

REV. 0

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