AD7398BR-REEL7 Просмотр технического описания (PDF) - Analog Devices

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AD7398BR-REEL7

Quad, Serial-Input 12-Bit/10-Bit DACs

Analog Devices 

AD7398/AD7399

Table I. Control Logic Truth Table

CS

CLK

LDAC

Serial Shift Register Function

Input Register Function

DAC Register

H

X

H

L

L

H

L

↑+

H

L

H

H

↑+

L/H

H

H

X

L

H

X

↑+

No Effect

No Effect

Shift-Register-Data Advanced One Bit

No Effect

No Effect

No Effect

No Effect

No Effect

No Effect

Latched

Latched

Updated with SR Contents

Latched

Latched

No Effect

No Effect

Latched

Latched

Latched

Transparent

Latched

NOTES

1. ↑+ Positive logic transition; ↓– Negative logic transition; X Don’t Care; SR shift register.

2. At power ON, both the Input Register and the DAC Register are loaded with all zeros.

3. During Power Shutdown, reprogramming of any internal registers can take place, but the output amplifiers will not produce the new values until the part is taken

out of Shutdown mode.

4. LDAC input is a level-sensitive input that controls the four DAC registers.

Table II. AD7398 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB

LSB

Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

AD7398

SA SD A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NOTE

Bit positions B14 and B15 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to

Logic 1, the address decoded by Bits B12 and B13 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.

Table III. AD7399 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB

LSB

Bit Position B13 B12 B11 B10 B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

AD7399

SA

SD

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NOTE

Bit positions B12 and B13 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to

Logic 1, the address decoded by Bits B10 and B11 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.

Table IV. AD7398/AD7399 Address Decode Control

SA

SD

A1

A0

1

X

X

X

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

DAC Channel Affected

All DACs Shutdown

DAC A Shutdown

DAC B Shutdown

DAC C Shutdown

DAC D Shutdown

DAC A Input Register Decoded

DAC B Input Register Decoded

DAC C Input Register Decoded

DAC D Input Register Decoded

–6–

REV. 0

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