AD7398BR-REEL7 Просмотр технического описания (PDF) - Analog Devices
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AD7398BR-REEL7 Datasheet PDF : 16 Pages
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AD7398/AD7399–SPECIFICATIONS
AD7398 12-BIT VOLTAGE OUTPUT DAC (@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40؇C < TA
< +125؇C, unless otherwise noted.)
Parameter
Symbol Condition
3 V–5 V ؎ 10% ؎5 V ؎ 10% Unit
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco3
REFERENCE INPUT
VREFIN Range4
Input Resistance5
Input Capacitance3
N
INL
DNL
VZSE
VFSE
TCVFS
VREF
RREF
CREF
Monotonic
Data = 000H
Data = FFFH
Data = 555H, Worst-Case
12
± 1.5
±1
7
± 2.5
1.5
0/VDD
35
5
12
± 1.5
±1
± 2.5
± 2.5
1.5
VSS/VDD
35
5
Bits
LSB max
LSB max
mV max
mV max
ppm/°C typ
V min/max
kΩ typ6
pF typ
ANALOG OUTPUT
Output Current
Capacitive Load3
IOUT
CL
Data = 800H, ∆VOUT = 4 LSB
±5
No Oscillation
200
±5
mA typ
400
pF max
LOGIC INPUTS
Logic Input Low Voltage
VIL
Logic Input High Voltage
VIH
Input Leakage Current
IIL
Input Capacitance3
CIL
VDD = 3 V
VDD = 5 V
CLK Only
0.5
0.8
0.8
80% VDD
4.0
2.1–2.4
2.4
1
1
10
10
V max
V max
V min
V min
µA max
pF max
INTERFACE TIMING3, 7
Clock Frequency
Clock Width High
Clock Width Low
CS to Clock Set Up
Clock to CS Hold
Load DAC Pulsewidth
Data Setup
Data Hold
Load Setup to CS
Load Hold to CS
fCLK
tCH
tCL
tCSS
tCSH
tLDAC
tDS
tDH
tLDS
tLDH
11
16.6
MHz max
45
30
ns min
45
30
ns min
10
5
ns min
20
15
ns min
45
30
ns min
15
10
ns min
10
5
ns min
0
0
ns min
20
15
ns min
AC CHARACTERISTICS
Output Slew Rate
Settling Time8
Shutdown Recovery
DAC Glitch
Digital Feedthrough
Feedthrough
SR
Data = 000H to FFFH to 000H
2
tS
To ± 0.1% of Full Scale
6
tSDR
6
Q
Code 7FFH to 800H to 7FFH
150
QDF
15
VOUT/VREF VREF = 1.5 VDC + 1 V p-p,
–63
Data = 000H, f = 100 kHz
2
V/µs typ
6
µs typ
6
µs typ
150
nVs typ
15
nVs typ
–63
dB typ
SUPPLY CHARACTERISTICS
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
IDD_SD
IDD
ISS
PDISS
PSS
No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = ± 5%
30/60
1.5/2.5
1.5/2.5
5
0.006
30/60
1.6/2.7
1.6/2.7
16
0.006
µA typ/max
mA typ/max
mA typ/max
mW typ
%/% max
NOTES
1One LSB = VREF/4096 V for the 12-bit AD7398.
2The first eight codes (000H, 007H) are excluded from the linearity error measurement in single supply operation.
3These parameters are guaranteed by design and not subject to production testing.
4When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Operation section of the data sheet.
5Input resistance is code-dependent.
6Typicals represent average readings measured at 25°C.
7All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
–2–
REV. 0
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