AD7294 Просмотр технического описания (PDF) - Analog Devices
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AD7294 Datasheet PDF : 45 Pages
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AD7294
Preliminary Technical Data
TIMING CHARACTERISTICS1,2
I2C Serial Interface
DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
FSCL
t1
t2
t3
t4
t5
t63
t7
t8
t9
t10
t11
Cb
Limit at TMIN, TMAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1Cb4
400
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data set-up time
tHD,DAT, data hold time
tHD,DAT, data hold time
tSU,STA, set-up time for repeated start
tSU,STO, stop condition set-up time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 Guaranteed by design and characterization; not subject to production test.
2 See Figure 2.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
4 Cb is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START
CONDITION
t6
t2
t5
t1
t7
REPEATED
START
CONDITION
Figure 2. I2C-Compatible Serial Interface Timing Diagram
200µA
IOL
TO OUTPUT PIN
CL
50pF
200µA
IOH
VOH (MIN) OR
VOL (MAX)
Figure 3. Load Circuit for Digital Output
Rev. PrB | Page 6 of 45
t8
STOP
CONDITION
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