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EVAL-CEDZ

1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators

Analog Devices 

AD7264

TERMINOLOGY

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

and the ideal 1 LSB change between any two adjacent codes in

the ADC.

Integral Nonlinearity (INL)

Integral nonlinearity is the maximum deviation from a straight

line passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a single

(1) LSB point below the first code transition, and full scale, a

point 1 LSB above the last code transition.

Zero Code Error

This is the deviation of the midscale transition (all 1s to all 0s)

from the ideal VIN voltage, that is, VCM − ½ LSB.

Positive Full-Scale Error

This is the deviation of the last code transition (011 … 110 to

011 … 111) from the ideal, that is,

VCM

+ ⎜⎛

⎝

VREF ⎟⎞

2 × Gain ⎠

− 1 LSB

after the zero code error has been adjusted out.

Negative Full-Scale Error

This is the deviation of the first code transition (10 … 000 to

10 … 001) from the ideal, that is,

VCM

−

⎜⎛

⎝

2

VREF

× Gain

⎟⎞

⎠

+

1

LSB

after the zero code error has been adjusted out.

Zero Code Error Match

This is the difference in zero code error across both ADCs.

Positive Full-Scale Error Match

This is the difference in positive full-scale error across both ADCs.

Negative Full-Scale Error Match

This is the difference in negative full-scale error across both ADCs.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end

of conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within ±1/2 LSB, after the end of conversion.

Signal-to-(Noise + Distortion) Ratio

This ratio is the measured ratio of signal-to-(noise + distortion)

at the output of the analog-to-digital converter. The signal is the

rms amplitude of the fundamental. Noise is the sum of all non-

fundamental signals up to half the sampling frequency (fS/2),

excluding dc. The ratio is dependent on the number of quan-

tization levels in the digitization process; the more levels, the

smaller the quantization noise.

The theoretical signal-to-(noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for a 14-bit converter, this is 86 dB.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of

harmonics to the fundamental. For the AD7264, it is defined as

THD(dB) = 20 log V2 2 + V32 + V4 2 + V5 2 + V6 2

V1

where V1 is the rms amplitude of the fundamental and V2, V3,

V4, V5, and V6 are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic, or spurious noise, is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to fS/2, excluding dc) to the rms value of the fun-

damental. Normally, the value of this specification is determined

by the largest harmonic in the spectrum, but for ADCs where

the harmonics are buried in the noise floor, it is a noise peak.

ADC-to-ADC Isolation

ADC-to-ADC isolation is a measure of the level of crosstalk

between ADC A and ADC B. It is measured by applying a full-

scale, 100 kHz sine wave signal to all unselected input channels and

determining how much that signal is attenuated in the selected

channel with a 40 kHz signal. The figure given is the worst-case.

Power Supply Rejection Ration (PSRR)

Variations in power supply affect the full-scale transition but

not the linearity of the converter. PSRR is the maximum change

in the full-scale transition point due to a change in power

supply voltage from the nominal value (see Figure 22).

Propagation Delay Time, Low to High (tPLH)

Propagation delay time from low to high is defined as the time

taken from the 50% point on a low to high input signal until the

digital output signal reaches 50% of its final low value.

Propagation Delay Time, High to Low (tPHL)

Propagation delay time from high to low is defined as the time

taken from the 50% point on a high to low input signal until the

digital output signal reaches 50% of its final high value.

Comparator Offset

Comparator offset is the measure of the density of digital 1s

and 0s in the comparator output when the negative analog

terminal of the comparator input is held at a static potential,

and the analog input to the positive terminal of the comparators

is varied proportionally about the static negative terminal voltage.

Rev. A | Page 14 of 32

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