EVAL-CED1Z(Rev0) Просмотр технического описания (PDF) - Analog Devices

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EVAL-CED1Z
(Rev.:Rev0)

1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators

Analog Devices 

Pin No.

23

35

48, 47, 46, 45

13, 14, 15, 16

5, 6, 8, 19, 42

28

30, 29, 26, 25

32, 31

40, 39, 38, 37

27

44, 17

24

AD7262

Mnemonic

PD0/DIN

CS

CA+, CA−,

CB+, CB−

CC+, CC−,

CD+, CD−

AGND

DGND

COUTA, COUTB,

COUTC, COUTD

DOUTA, DOUTB

G0, G1, G2, G3

VDRIVE

CA_CB_GND,

CC_CD_GND

REFSEL

Description

Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction

with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts

as the data input pin, and all programming is via the control register (see Table 8). Data to be written

to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register

on the falling edge of SCLK.

Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5.

Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A

and Comparator B. These two comparators have very low power consumption.

Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C

and Comparator D. This pair of comparators offers very fast propagation delays.

Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. All

analog input signals and any external reference signal should be referred to this AGND voltage.

All AGND pins should connect to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and

CC_CD_GND voltages ideally should be at the same potential and must not be more than 0.3 V apart,

even on a transient basis. CA_CB_GND and CC_CD_GND can be tied to AGND.

Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5.

The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages

should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient

basis.

Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective

comparator. These are digital output pins with logic levels determined by the VDRIVE supply.

Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial

data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK

input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During

the conversion process, the data output pins are in three-state and, when the conversion is

completed, the 19th SCLK edge clocks out the MSB. The data simultaneously appears on both pins

from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for

an additional 12 SCLK cycles on either DOUTA or DOUTB following the initial 31 SCLKs, the data from

the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both

ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port.

Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four

pins are tied low, the PD0 pin acts as a data input pin, DIN, and all programming is made via the

control register (see Table 6).

Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what

voltage the interface operates, including the comparator outputs. This pin should be decoupled to

DGND.

Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/

AD7262-5. Both the CA_CB_GND pin and the CC_CD_GND pin should connect to the GND plane of a

system and can be tied to AGND. The DGND, AGND, CA_CB_GND, and CC_CD_GND voltages should

ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on-

chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is

tied to GND, an external reference can be supplied to the AD7262/AD7262-5 through the VREFA

and/or VREFB pin.

Rev. 0 | Page 9 of 32

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