WM8729 Просмотр технического описания (PDF) - Wolfson Microelectronics plc
Номер в каталоге
Компоненты Описание
производитель
WM8729 Datasheet PDF : 15 Pages
| |||
WM8729
Product Preview
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
LRCIN
BCKIN
LEFT CHANNEL
1/fs
RIGHT CHANNEL
DIN
123
n-2 n-1 n
123
n-2 n-1 n
MSB
LSB
MSB
LSB
Figure 3 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left samples and high during the right samples.
1/fs
LRCIN
LEFT CHANNEL
RIGHT CHANNEL
BCKIN
DIN
1 BCKIN
123
MSB
n-2 n-1 n
LSB
1 BCKIN
123
MSB
n-2 n-1 n
LSB
Figure 4 I2S Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8729 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8729 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCIN, although the WM8729 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
(LRCIN)
128fs
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
192fs
256fs
384fs
512fs
32kHz
44.1kHz
4.096
5.6448
6.144
8.467
8.192
11.2896
12.288
16.9340
16.384
22.5792
48kHz
96kHz
192kHz
6.114
12.288
24.576
9.216
18.432
36.864
12.288
18.432
24.576
24.576
36.864 Unavailable
Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
768fs
24.576
33.8688
36.864
Unavailable
Unavailable
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
8
Share Link: 