AD679JNZ Просмотр технического описания (PDF) - Analog Devices
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AD679JNZ Datasheet PDF : 16 Pages
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AD679
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both chip select (CS)
and start convert (SC) must be brought LOW to start a conver-
sion. CS should be LOW tSC before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC low, regardless of the state of CS.
Before a conversion is started, end-of-convert (EOC) is HIGH
and the sample-and-hold is in track mode. After a conversion is
started, the sample-and-hold goes into hold mode and EOC
goes LOW, signifying that a conversion is in progress. During
the conversion, the sample-and-hold will go back into track
mode and start acquiring the next sample.
In track mode, the sample-and-hold will settle to Ϯ0.003%
(14 bits) in 1.5 µs maximum. The acquisition time does not
affect the throughput rate as the AD679 goes back into track
mode more than 2 µs before the next conversion. In multichan-
nel systems, the input channel can be switched as soon as EOC
goes LOW.
Bringing OE LOW tOE after CS goes LOW makes the output
register contents available on the output data bits (DB7–DB0).
A period of time, tCD, is required after OE is brought HIGH
before the next SC instruction is issued.
If SC is held LOW, conversion accuracy may deteriorate. For
this reason, SC should not be held low in an attempt to operate
in a continuously converting mode.
Table I. Start Conversion Truth Table
Inputs
SYNC CS SC Status
Synchronous
1
1 X No Conversion
Mode
1
0 f Start Conversion
1
f 0 Start Conversion
(Not Recommended)
1
0 0 Continuous Conversion
(Not Recommended)
Asynchronous 0
Mode
0
0
X 1 No Conversion
X f Start Conversion
X 0 Continuous Conversion
(Not Recommended)
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
f = HIGH to LOW transition. Must stay low for t = tCP.
Table II. 14-Bit Mode Coding Format (1 LSB = 0.61 mV)
Unipolar Coding
(Straight Binary)
VIN*
Output Code
0.00000 V
5.00000 V
9.99939 V
000 . . . 0
100 . . . 0
111 . . . 1
*Code center.
Bipolar Coding
(Twos Complement)
VIN* (V)
Output Code
–5.00000
–0.00061
0.00000
+2.50000
+4.99939
100 . . . 0
111 . . . 1
000 . . . 0
010 . . . 0
011 . . . 1
END-OF-CONVERT
In asynchronous mode, end-of-convert (EOC) is an open-drain
output (requiring a minimum 3 kΩ pull-up resistor) enabled by
end-of-convert enable (EOCEN). In synchronous mode, EOC
is a three-state output that is enabled by EOCEN and CS. See
Table III. Access (tBA) and float (tFD) timing specifications do
not apply in asynchronous mode where they are a function of
the time constant formed by the external load capacitance and
the pull-up resistor.
OUTPUT ENABLE OPERATION
The data bits (DB7–DB0) are three-state outputs that are enabled
by chip select (CS) and output enable (OE). CS should be
LOW tOE before OE is brought LOW.
When EOC goes HIGH, the conversion is completed and the
output data may be read. The output is read in two steps as a
16-bit word, with the high byte read first, followed by the low
byte. High byte enable (HBE) controls the output sequence.
The 14-bit result is left justified within the 16-bit field.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT),
output coding is twos complement binary.
POWER-UP
The AD679 typically requires 10 µs after power-up to reset
internal logic.
Table III. Conversion Status Truth Table
Inputs
Output
SYNC CS EOCEN EOC
Status
Synchronous 1 0
Mode
10
11
1X
00
Converting
01
Not Converting
X High Z Either
1 High Z Either
Asynchronous 0 X
Mode*
0X
0X
00
Converting
0 High Z Not Converting
1 High Z Either
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
*EOC requires a pull-up resistor in asynchronous mode.
Table IV. Output Enable Truth Table
Unipolar or
Bipolar
Inputs
HBE (CS U OE)
Outputs
DB7 . . . DB0
X
1
← High Z →
0
0
1
0
abcdefgh
i j k l mn00
1 = HIGH voltage level. a = MSB.
0 = LOW voltage level. n = LSB.
X = Don’t care.
U = Logical OR.
Data coding is binary for unipolar mode and twos complement binary for
bipolar mode.
REV. D
–9–
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