AD671SD-750 Просмотр технического описания (PDF) - Analog Devices
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AD671SD-750 Datasheet PDF : 16 Pages
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AD671
+15V ±5V
2
AD586 +VIN
8 U4
VOUT
NOISE
6
1µF
REDUCTION 6.8µF
C14
GND
C15
4
23 24 17
VCC VEE VLOGIC
20 AIN
BIT1 1
U3
BIT12 12
22 ACOM ENCODE 16
18 DCOM
DAV 15
19 REF IN
OTR 14
21 BPO/UPO MSB 13
AD671
Table I. Grounding and Decoupling Guidelines
Power Supply
Decoupling
Capacitor Values
Comment
0.1 µF (Ceramic) and 10 µF (Tantalum).
(Surface Mount Chip Capacitors Recom-
mended to Reduce Lead Inductance).
Capacitor Locations Directly at Positive and Negative
Supply Pins to Respective Ground Plane.
Grounding
Analog Ground
Ground Plane or Wide Ground Return
OBSOLETE Figure 5. AD586 as Reference Input for AD671
GROUNDING AND DECOUPLING RULES
Proper grounding and decoupling should be a primary design
objective in any high speed, high resolution system. The AD671
separates analog and digital grounds to optimize the manage-
ment of analog and digital ground currents in a system. The
AD671 is designed to minimize the current flowing from
ACOM (Pin 22) by directing the majority of the current from
VCC (+5 V–Pin 23) to VEE (–5 V–Pin 24). Minimizing analog
ground currents hence reduces the potential for large ground
voltage drops. This can be especially true in systems that do not
utilize ground planes or wide ground runs. ACOM is also con-
figured to be code independent, therefore reducing input depen-
dent analog ground voltage drops and errors. The input current
supplied by the external reference (REFIN–Pin 19) and the ma-
Digital Ground
Analog and Digital
Ground
Connected to the Analog Power Supply.
Ground Plane or Wide Ground Return
Connected to the Digital Power Supply.
Connected Together Once at the AD671.
UNIPOLAR (0 V TO +10 V) CALIBRATION
The AD671 is factory trimmed to minimize offset, gain and lin-
earity errors. In some applications the offset and gain errors of
the AD671 need to be externally adjusted to zero. This is ac-
complished by trimming the voltage at BPO/UPO (Pin 21) and
REFIN (Pin 19). In those applications the AD588, a high preci-
sion pin programmable voltage reference, is an ideal choice. The
AD588 includes a reference cell and three additional amplifiers
which can be configured to provide offset and gain trims for the
jority of the full-scale input signal (AIN–Pin 20) are also di-
AD671. The circuit in Figure 7 is recommended for calibrating
rected to VÉE. Also critical in any high speed digital design are
offset and gain errors of the AD671 when configured in the 0 V
the use of proper digital grounding techniques to avoid potential to +10 V input range.
CMOS “ground bounce.” Figure 6 is provided to assist in the
proper layout, grounding and decoupling techniques.
+5V –5V +5V
Table I is a list of grounding and decoupling guidelines that
10µF 10µF 10µF
should be reviewed before laying out a printed circuit board.
0.1µF 0.1µF 0.1µF
+5V –5V +5V
10µF 10µF 10µF
+15V
39k
23
VCC
0 TO +10V
20 AIN
24
VEE
17
VLOGIC
BIT1 12
R1
BIT12 1
100
22 ACOM ENCODE 16
0.1µF 0.1µF 0.1µF
23
24
17
VCC VEE
VLOGIC
+
20 AIN
BIT1 12
VIN ±5V
–
AGP*
DGP*
BIT12 1
22 ACOM
18 DCOM
ENCODE 16
DAV 15
150pF
1µF
7
6
4
3
50
1
10µF
14
AD588
1µF 10k
15
150 10µF
2 +15
16 –15
5 9 10 8 12 11 13
100k
R2
5k
50
18 DCOM
DAV 15
19 REF IN
0.1µF
21 BPO/UPO
OTR 14
MSB 13
0.1µF
AD671
+5V REF
19 REF IN
OTR 14
21 BPO/UPO MSB 13
AD671
*GROUND PLANE RECOMMENDED
Figure 6. AD671 Grounding and Decoupling
Figure 7. Unipolar (0 V to +10 V) Calibration
The AD671 is intended to have a nominal 1/2 LSB offset so
that the exact analog input for a given code will be in the middle
of that code (halfway between the transitions to the codes above
it and below it). Thus, the first transition ( from 0000 0000 0000
to 0000 0000 0001) will occur for an input level of +1/2 LSB
(1.22 mV for 10 V range). If the offset trim resistor R2 is used,
REV. B
–9–
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