AD671JD-500 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD671JD-500

Monolithic 12-Bit 2 MHz A/D Converter

Analog Devices 

AD671

DEFINITIONS OF SPECIFICATIONS

GAIN ERROR

INTEGRAL NONLINEARITY (INL)

The last transition (from 1111 1111 1110 to 1111 1111 1111)

Integral nonlinearity refers to the deviation of each individual

should occur for an analog value 1 1/2 LSB below the nominal

code from a line drawn from “zero” through “full scale.” The

full scale (9.9963 volts for 10.000 volts full scale). The gain er-

point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span) ror is the deviation of the actual level at the last transition from

before the first code transition (all zeros to only the LSB on).

the ideal level. The gain error can be adjusted to zero as shown

“Full scale” is defined as a level 1 1/2 LSB beyond the last code in Figures 7, 8 and 9.

transition (to all ones). The deviation is measured from the low

side transition of each particular code to the true straight line.

TEMPERATURE COEFFICIENTS

The temperature coefficients for unipolar offset, bipolar zero

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING

and gain error specify the maximum change from the initial

CODES)

(+25°C) value to the value at TMIN or TMAX.

An ideal ADC exhibits code transitions that are exactly 1 LSB

OBSOLETE apart. DNL is the deviation from this ideal value. Thus every

code must have a finite width. Guaranteed no missing codes to

10-bit resolution indicates that all 1024 codes represented by

Bits 1–10 must be present over all operating ranges. Guaranteed

no missing codes to 11- or 12-bit resolution indicates that all

2048 and 4096 codes, respectively, must be present over all op-

erating ranges.

UNIPOLAR OFFSET

The first transition should occur at a level 1/2 LSB above analog

common. Unipolar offset is defined as the deviation of the ac-

tual from that point. This offset can be adjusted as discussed

later. The unipolar offset temperature coefficient specifies the

maximum change of the transition point over temperature, with

or without external adjustments.

BIPOLAR ZERO

In the bipolar mode the major carry transition (0111 1111 1111

POWER SUPPLY REJECTION

The only effect of power supply error on the performance of the

device will be a small change in gain. The specifications show

the maximum full-scale change from the initial value with the

supplies at the various limits.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO

S/N+D is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components, including har-

monics but excluding dc. The value for S/N+D is expressed in

decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

ENOB is calculated from the expression SNR = 6.02N +

1.8 dB, where N is equal to the effective number of bits.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic com-

to 1000 0000 0000) should occur for an analog value 1/2 LSB

ponents to the rms value of the measured input signal and is ex-

below analog common. The bipolar offset error and temperature pressed as a percentage or in decibels.

coefficient specify the initial deviation and maximum change in

the error over temperature.

PEAK SPURIOUS OR PEAK HARMONIC COMPONENT

The peak spurious or peak harmonic component is the largest

spectral component excluding the input signal and dc. This

value is expressed in decibels relative to the rms value of a full-

scale input signal.

Theory of Operation

The AD671 uses a successive subranging architecture. The ana-

log to digital conversion takes place in four independent steps or

flashes. The analog input signal is subranged to an intermediate

residue voltage for the final 12-bit result by utilizing multiple

flashes with subtraction DACs (see the AD671 functional block

diagram).

The AD671 can be configured to operate with unipolar (0 V to

+5 V, 0 V to +10 V) or bipolar (± 5 V) inputs by connecting

AIN (Pin 20), REFIN (Pin 19) and BPO/UPO (Pin 21) as

shown in Figure 2.

The AD671 conversion cycle begins by simply providing an ac-

tive HIGH pulse on the ENCODE pin (Pin 16). The rising

edge of the ENCODE pulse starts the conversion. The falling

edge of the ENCODE pulse is specified to operate within a win-

dow of time: less than 30 ns after the rising edge of ENCODE

(AD671-500) and less than 50 ns after the falling edge of

ENCODE (AD671–750) or after the falling edge of DAV. The

time window prevents digitally coupled noise from being intro-

duced during the final stages of conversion. An internal timing

generator circuit accurately controls all internal timing.

ACOM 22

BPO/UPO 21

AIN 20

AIN

REF IN 19 +5V REF

0 TO +5V

BPO/UPO 21

AIN 20

AIN

REF IN 19

+5V REF

0 TO +10V

BPO/UPO 21

AIN 20

AIN

REF IN 19

+5V REF

–5V TO +5V

Figure 2. Input Range Connections

REV. B

–7–

Share Link: