AD671 Просмотр технического описания (PDF) - Analog Devices
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AD671 Datasheet PDF : 16 Pages
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AD671
it should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give ap-
proximately ± 50 mV of offset trim range.
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (9.9963 for a 10 V range). Trim R1 to give
the last transition (1111 1111 1110 to 11111111 1111).
Bipolar calibration is similar to unipolar calibration. First, a sig-
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963) is applied, and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
UNIPOLAR (0 V TO +5 V) CALIBRATION
OUTPUT LATCHES
The connections for the 0 V to +5 V input range calibration is
Figure 10 shows the AD671 connected to the 74HC574 Octal
shown in Figure 8. The AD586, a +5 V precision voltage refer- D-type edge triggered latches with 3-state outputs. The latch
ence, is an excellent choice for this mode of operation because
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
of its performance, stability and optional fine trim. The AD845 maintaining the data signal integrity. The maximum set-up and
(16 MHz, low power, low cost op amp) is used to maintain the
hold times of the 574 type latch must be less than 20 ns (tDD
OBSOLETE +5 volts under the dynamically changing load conditions of the
reference input.
+15V
0.1µF
2
7
0 TO +5V
3
AD845
8
4 1 1kΩ
6
+15V
2
+VIN
–15V
390
0.1µF
+15V
VOUT 6
27
AD845
34
0.1µF
6
8 NOISE TRIM 5
REDUCTION
10kΩ
0.1µF
–15V
23 24
VCC VEE
20 AIN
21 BPO/UPO
+15V
17
VLOGIC
BIT1 12
BIT12 1
22 ACOM ENCODE 16
18 DCOM
DAV 15
19 REFIN
OTR 14
MSB 13
AD671
1µF
AD586
GND
4
Figure 8. Unipolar (0 V to +5 V) Calibration
and tSS minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are HC, S, AS, ALS, F or
BCT. New data from the AD671 is latched on the rising edge of
the DAV (Pin 24) output pulse. Previous data can be latched by
inverting the DAV output with a 7404 type inverter. See Fig-
ures 20, 21 and 22 for PCB layout recommendations.
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
DAV
BIT9
BIT10
BIT11
BIT12
74HC574
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D U6 5Q
6D
6Q
7D
7Q
8D
8Q
CLK OC
74HC574
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D U5 5Q
DATA BUS
The AD671 offset error must be trimmed within the analog in-
6D
6Q
7D
7Q
put path, either directly in front of the AD671 or within the sig-
nal conditioning chain, eliminating offset errors induced by the
AD671
8D
8Q
CLK
OC
3-STATE
CONTROL
signal conditioning circuitry. Figure 8 shows an example of how
the offset error can be trimmed in front of the AD671. The
Figure 10. AD671 to Output Latches
AD586 is configured in the optional fine trim mode to provide
+6%/–2% (+240 LSBs/–80 LSBs) of gain trim. The procedure
for trimming the offset and gain errors is similar to that used for
the unipolar 10 V range with the analog input values set to one-
half the 10 V range values.
OUT OF RANGE
An Out of Range condition exists when the analog input voltage
is beyond the input range (0 V to +5 V, 0 V to +10 V, ± 5 V) of
the converter. OTR (Pin 14) is set low when the analog input
voltage is within the analog input range. OTR is set HIGH and
BIPOLAR (؎5 V) CALIBRATION
The connections for the bipolar input range is shown in Figure
9. The AD588 is configured to provide dual +5 V outputs. Pro-
viding a +5 V reference voltage for the AD671 gain trim and the
+5 V BPO/UPO input for the bipolar offset trim.
will remain HIGH when the analog input voltage exceeds the
input range by typically 1/2 LSB (OTR transition is tested to
± 6 LSBs of accuracy) from the center of the ± full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement overrange
+15V
6.2kΩ R1
100
39k
23
24
17
± 5V
VCC VEE
20 AIN
VLOGIC
BIT1 12
BIT12 1
22 ACOM ENCODE 16
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 11. Sys-
tems requiring programmable gain conditioning prior to the
AD671 can immediately detect an out of range condition, thus
eliminating gain selection iterations.
150pF
1µF
7
6
4
3
50
1
14
10µF
AD588
150pF
R2
100
15
50 10µF
2 +15
16 –15
5 9 10 8 12 11 13
18 DCOM
DAV 15
19 REF IN
0.1µF
21 BPO/UPO
OTR 14
MSB 13
AD671
0.1µF
Table II. Out of Range Truth Table
OTR
MSB
Analog Input Is
0
0
In Range
0
1
In Range
1
0
Underrange
1
1
Overrange
Figure 9. Bipolar (±5 V) Calibration
–10–
REV. B
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