AD6655-150EBZ1 Просмотр технического описания (PDF) - Analog Devices

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производитель

AD6655-150EBZ1

IF Diversity Receiver

Analog Devices 

AD6655

DIGITAL SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,

DCS enabled, unless otherwise noted.

Table 6.

Parameter

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

Input Resistance

SYNC INPUT

Logic Compliance

Internal Bias

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

Input Resistance

LOGIC INPUT (CSB)1

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Input Capacitance

LOGIC INPUT (SCLK/DFS)2

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Input Capacitance

LOGIC INPUTS (SDIO/DCS, SMI SDFS)1

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Input Capacitance

Temp

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

AD6655BCPZ-125

Min

Typ Max

CMOS/LVDS/LVPECL

1.2

0.2

6

AVDD − 0.3

AVDD + 1.6

1.1 V

AVDD

1.2

3.6

0

0.8

−10

+10

−10

+10

4

8

10

12

AVDD − 0.3

1.2

0

−10

−10

8

CMOS

1.2

4

10

AVDD + 1.6

3.6

0.8

+10

+10

12

1.22

3.6

0

0.6

−10

+10

40

132

26

2

1.22

3.6

0

0.6

−92

−135

−10

+10

26

2

1.22

3.6

0

0.6

−10

+10

38

128

26

5

AD6655BCPZ-150

Min

Typ Max

CMOS/LVDS/LVPECL

1.2

0.2

6

AVDD − 0.3

AVDD + 1.6

1.1 V

AVDD

1.2

3.6

0

0.8

−10

+10

−10

+10

4

8

10

12

AVDD − 0.3

1.2

0

−10

−10

8

CMOS

1.2

4

10

AVDD + 1.6

3.6

0.8

+10

+10

12

1.22

3.6

0

0.6

−10

+10

40

132

26

2

1.22

3.6

0

0.6

−92

−135

−10

+10

26

2

1.22

3.6

0

0.6

−10

+10

38

128

26

5

Unit

V

V p-p

V

V

V

V

μA

μA

pF

kΩ

V

V

V

V

μA

μA

pF

kΩ

V

V

μA

μA

kΩ

pF

V

V

μA

μA

kΩ

pF

V

V

μA

μA

kΩ

pF

Rev. 0 | Page 11 of 84

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