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AD6650BBC

Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver

Analog Devices 

AD6650

ELECTRICAL CHARACTERISTICS

Table 3.

Parameter (Conditions)

LOGIC INPUTS

Logic Compatibility

Digital Logic

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

Input Capacitance

CLOCK INPUTS

Differential Input Voltage1

Common-Mode Input Voltage

Differential Input Resistance

Differential Input Capacitance

LOGIC OUTPUTS

Logic Compatibility

Logic 1 Voltage (IOH = 0.25 mA)

Logic 0 Voltage (IOL = 0.25 mA)

IDD SUPPLY CURRENT

CLK = 52 MHz (GSM Example)

IDVDD

IAVDD

POWER DISSIPATION

CLK = 52 MHz (GSM/EDGE Example)

Temp

Full

Full

Full

25°C

25°C

25°C

25°C

25°C

25°C

25°C

Full

Full

Full

Test Level

IV

IV

IV

V

V

V

V

V

V

V

IV

IV

Min Typ

3.3 V CMOS

2.0

0

60

7

5

0.4

DVDD/2

7.5

5

3.3 V CMOS/TTL

2.4

VDD − 0.2

0.2

Full

VII

155

Full

VII

360

Full

VII

1.7

Max Unit

VDD V

0.8

V

μA

μA

pF

3.6

V p-p

V

kΩ

pF

V

0.8

V

mA

mA

2.1

W

1 All ac specifications are tested by driving CLK and CLK differentially.

GENERAL TIMING CHARACTERISTICS

Table 4.

Parameter (Conditions)

CLK TIMING REQUIREMENTS

CLK Period1

CLK Width Low

CLK Width High

RESET TIMING REQUIREMENTS

RESET Width Low

PIN_SYNC TIMING REQUIREMENTS

SYNC to ↑ CLK Setup Time

SYNC to ↑ CLK Hold Time

SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS2

↑ CLK to ↑ SCLK Delay (Divide-by-1)

↑ CLK to ↑ SCLK Delay (For Any Other Divisor)

↑ CLK to ↓ SCLK Delay (Divide-by-2 or Even Number)

↓ CLK to ↓ SCLK Delay (Divide-by-3 or Odd Number)

↑ SCLK to SDFS Delay

↑ SCLK to SDO0 Delay

↑ SCLK to SDO1 Delay

↑ SCLK to DR Delay

Symbol Temp Test Level Min Typ

Max Unit

tCLK

tCLKL

tCLKH

Full I

Full IV

Full IV

9.6

19.2 ns

0.5 × tCLK

ns

0.5 × tCLK

ns

tSSF

Full IV

30

ns

tSS

Full IV

−3

ns

tHS

Full IV

6

ns

tDSCLK1

Full

IV

3.2

tDSCLKH

Full

IV

4.4

tDSCLKL

Full

IV

4.7

tDSCLKLL

Full

IV

4

tDSDFS

Full IV

1

tDSDO0

Full IV

0.5

tDSDO1

Full IV

0.5

tDSDR

Full IV

1

12.5 ns

16 ns

16 ns

14 ns

2.6 ns

3.5 ns

3.5 ns

3.5 ns

1 Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a

52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS.

2 The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1.

Rev. A | Page 5 of 44

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