AD6650(2003) Просмотр технического описания (PDF) - Analog Devices
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AD6650 Datasheet PDF : 28 Pages
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Preliminary Technical Data
MICROPROCESSOR PORT TIMING CHARACTERISTICS1
Test
Temp Level Min
AD6650
Typ
AD6650
Max Units
MICROPROCESSOR PORT, MODE INM (MODE=0)
MODE INM Write Timing:
tSC
Control3 to ↑CLK Setup Time
tHC
Control3 to ↑CLK Hold Time
tHWR
/WR(RW) to RDY(/DTACK) Hold Time
tSAM
Address/Data to /WR(RW) Setup Time
tHAM
Address/Data to RDY(/DTACK) Hold Time
tDRDY
/WR(RW) to RDY(/DTACK) Delay
tACC
/WR(RW) to RDY(/DTACK) High Delay
MODE INM Read Timing:
tSC
Control3 to ↑CLK Setup Time
tHC
Control3 to ↑CLK Hold Time
tSAM
Address to /RD(/DS) Setup Time
tHAM
Address to Data Hold Time
tZD
Data Tri-state Delay
tDD
RDY(/DTACK) to Data Delay
tDRDY
/RD(/DS) to RDY(/DTACK) Delay
tACC
/RD(/DS) to RDY(/DTACK) High Delay
MICROPROCESSOR PORT, MODE MNM (MODE=1)
Full IV
5.5
Full IV
1.0
Full IV
8.0
Full IV
-0.5
Full IV
7.0
Full IV
4.0
Full
IV 4*tCLK
Full
Full
Full
Full
Full
Full
Full
Full
Temp
IV
IV
IV
IV
IV
IV
IV
IV
Test
Level
4.0
2.0
0.0
7.0
4.0
4*tCLK
Min
AD6650
Typ
MODE MNM Write Timing:
tSC
Control3 to ↑CLK Setup Time
Full IV
5.5
tHC
Control3 to ↑CLK Hold Time
Full IV
1.0
tHDS
/DS(/RD) to /DTACK(RDY) Hold Time
Full IV
8.0
tHRW
RW(/WR) to /DTACK(RDY) Hold Time
tSAM
Address/Data To RW(/WR) Setup Time
tHAM
Address/Data to RW(/WR) Hold Time
tDDTACK
/DS(/RD) to /DTACK(RDY) Delay
tACC
RW(/WR) to /DTACK(RDY) Low Delay
MODE MNM Read Timing:
Full IV
8.0
Full IV
-0.5
Full IV
7.0
Full IV
Full
IV 4*tCLK
tSC
Control3 to ↑CLK Setup Time
Full IV
4.0
tHC
Control3 to ↑CLK Hold Time
Full IV
2.0
tHDS
/DS(/RD) to /DTACK(RDY) Hold Time
Full IV
8.0
tSAM
Address to /DS(/RD) Setup Time
tHAM
Address to Data Hold Time
tZD
Data Tri-State Delay
tDD
/DTACK(RDY) to Data Delay
tDDTACK
/DS(/RD) to /DTACK(RDY) Delay
tACC
/DS(/RD) to /DTACK(RDY) Low Delay
MODE I2C Timing:
Full IV
0.0
Full IV
7.0
Full IV
Full IV
Full IV
Full
IV 4*tCLK
tDSCL
↑SCL to SDA Delay
Full IV
61
tDSDA
SDA to ↑SCL Delay
Full IV
57
tSSCL5
↑CLK to ↑SCL Delay
Full IV
5
1All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V.
2The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1)
3Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS
4(CLOAD=40pF on all outputs unless otherwise specified)
5There is no hold time for SDA because as this waits for a negative transition (↓) on SCL to transition.
5*tCLK
7*tCLK
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
5*tCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
7*tCLK
ns
ns
ns
ns
REV. PrJ 02/27/2003
7
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