AD6636CBCZ Просмотр технического описания (PDF) - Analog Devices
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AD6636CBCZ Datasheet PDF : 80 Pages
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AD6636
SERIAL PORT TIMING CHARACTERISTICS1, 2, 3
Table 5.
Parameter
SERIAL PORT CLOCK TIMING REQUIREMENTS
tSCLK
tSCLKL
SCLK Period
SCLK Low Time
tSCLKH
SCLK High Time
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
tSSDI
SDI to ↑SCLK Setup Time
tHSDI
SDI to ↑SCLK Hold Time
tSSCS
SCS to ↑SCLK Setup Time
tHSCS
SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
tSSDI
SDI to ↑SCLK Setup Time
tHSDI
SDI to ↑SCLK Hold Time
tSSRFS
SRFS to ↓SCLK Setup Time
tHSRFS
SRFS to ↓SCLK Hold Time
tSSTFS
STFS to ↓SCLK Setup Time
tHSTFS
STFS to ↑SCLK Hold Time
tSSCS
SCS to ↑SCLK Setup Time
tHSCS
SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
Temp Test Level
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Min
10.0
1.60
1.60
1.30
0.40
4.12
−2.78
4.28
0.80
0.40
1.60
−0.13
1.60
−0.30
4.12
−2.76
4.29
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
3 SCLK rise/fall time should be 3 ns maximum.
Typ
0.5 × tSCLK
0.5 × tSCLK
Max
7.96
7.95
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
EXPLANATION OF TEST LEVELS FOR SPECIFICATIONS
Table 6.
Test Level
Description
I
100% production tested.
II
100% production tested at 25°C, and sample tested at specified temperatures.
III
Sample tested only.
IV
Parameter guaranteed by design and analysis.
V
Parameter is typical value only.
VI
100% production tested at 25°C, and sampled tested at temperature extremes.
Rev. A | Page 9 of 80
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