AD6636(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD6636 Datasheet PDF : 72 Pages
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AD6636
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A GND
INC3
IND4
IND7
CLKD
CLKC
IND11
GND VDDCORE IND14
IND15
SYNC1
TDO PBGAIN PB11
16
GND A
B IND0
VDDIO
INC2
IND5
IND6
IND8
IND10
IND12
IND13
INC14 SYNC3 SYNC0
TRST
PBCH2 VDDIO
PB12 B
C EXPA1 EXPD1
INC0
INC1
IND3
INC5
IND9
INC10
INC13 SYNC2
TMS
TCLK PBCH0
PB8
PB15
PB10 C
D EXPB0 EXPC2 EXPC1 EXPD0
IND2
INC4
INC7
INC9
INC12
TDI
PBCH1
PBIQ
PB14
PB9
PB13
PACH1 D
E INA14
INA15
EXPA0 LVDS_RSET GND
IND1
INC6
INC8
INC11
INC15 PBREQ PBACK
PB4
PB5
PB1
PCLK E
F INA12
INA13 EXPB1 EXPC0 EXPD2
GND
VDDIO VDDIO VDDIO VDDIO
GND
PB6
PB0
PB7
PAREQ
PA0 F
G INA11
INB13
INB15
EXPB2 EXPA2 VDDCORE GND
GND
GND
GND VDDCORE PB3
PAGAIN
PB2
PACH0
PA2 G
H VDDCORE INA10
INB12
INB11
INB14 VDDCORE GND
GND
GND
GND VDDCORE PACH2
PAIQ
PAACK
PA1
GND H
J GND
INA9
INB10
INB8
INB9 VDDCORE GND
GND
GND
GND VDDCORE PA3
PA7
PA5
PA4 VDDCORE J
K CLKA
INA8
INA7
INB6
INB7 VDDCORE GND
GND
GND
GND VDDCORE PA12
PA15
PA9
PA8
PA6 K
L CLKB
INA6
INB4
INB1
INB3
GND
VDDIO VDDIO VDDIO VDDIO
GND
PC3
PCACK PCCH1
PA13
PA10 L
M INA5
INB5
INB2
INB0
GND
DTACK
(RDY, SDO)
D13
D15
D5
A5
PC12
PC7
PC2
PC0
PCCH0
PA11 M
N INA4
INA3
INA0
R/W (WR,
STFS)
CS (SCS)
CHIPID2
D12
D2
D1
A4
A0 (SDI) PC15
PC5
PC1
PCCH2
PA14 N
P INA2
INA1
RESET
DS (RD,
SRFS)
SMODE
CHIPID3
GND
D9
D4
A6
A2
PC11
PC10
PC4
PCIQ PCGAIN P
R
CPUCLK
(SCLK)
VDDIO
MSB_
FIRST
EXT_
FILTER
CHIPID1
D14
D10
D11
D6
D0
A3
A1
PC9
PC6
VDDIO PCREQ R
T GND
IRP
MODE CHIPID0
D7
D8
D3 VDDCORE GND
GND
A7
PC14
PC13
PC8
GND
GND T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
= VDDCORE
= VDDIO
= GROUND
Table 7. Pin Names and Functions
Name
Type
Pin No.
POWER SUPPLY
VDDCORE
Power
See Table 8
VDDIO
Power
See Table 8
GND
Ground
See Table 8
INPUT (ADC) PORTS (CMOS/LVDS)
CLKA
Input
K1
CLKB
CLKC
CLKD
INA[0:15]
INB[0:15]
INC[0:15]
IND[0:15]
EXPA[0:2]
EXPB[0:2]
EXPC[0:2]
EXPD[0:2]
CLKA, CLKB
Input
Input
Input
Input
Input
Input
Input
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input
L1
A6
A5
See Table 8
See Table 8
See Table 8
See Table 8
E3, C1, G5
D1, F3, G4
F4, D3, D2
D4, C2, F5
K1, L1
Figure 2. CSP_BGA Pin Configuration
Function
1.8 V Digital Core Supply.
3.3 V Digital I/O Supply.
Digital Core and I/O Ground.
Clock for Input Port A. Used to clock INA[15:0] and EXPA[2:0] data. Additionally,
this clock is used to drive internal circuitry and PLL clock multiplier.
Clock for Input Port B. Used to clock INB[15:0] and EXPB[2:0] data.
Clock for Input Port C. Used to clock INC[15:0] and EXPC[2:0] data.
Clock for Input Port D. Used to clock IND[15:0] and EXPD[2:0] data.
Input Port A (Parallel).
Input Port B (Parallel).
Input Port C (Parallel).
Input Port D (Parallel).
Exponent Bus Input Port A. Gain control output.
Exponent Bus Input Port B. Gain control output.
Exponent Bus Input Port C. Gain control output.
Exponent Bus Input Port D. Gain control output.
LVDS Differential Clock for LVDS_A Input Port (LVDS_CLKA+, LVDS_CLKA−).
Rev. 0 | Page 10 of 72
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