AD654 Просмотр технического описания (PDF) - Analog Devices

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AD654

Low Cost Monolithic Voltage-to-Frequency Converter

Analog Devices 

AD654

(OPTIONAL)

C

AD654

RCOMP

R1 R2

VIN

Figure 3b. Bias Current Compensation—Negative Inputs

If the AD654’s 1 mV offset voltage must be trimmed, the trim

must be performed external to the device. Figure 3c shows an

optional connection for positive inputs in which ROFF1 and

ROFF2 add a variable resistance in series with RT. A variable

source of ± 0.6 V applied to ROFF1 then adjusts the offset ± 1 mV.

Similarly, a ± 0.6 V variable source is applied to ROFF in Fig-

ure 3d to trim offset for negative inputs. The ±0.6 V bipolar

source could simply be an AD589 reference connected as shown

in Figure 3e.

10k⍀

VIN

ROFF2

20⍀ 5k⍀ 8.25k⍀

AD654

ROFF1

10k⍀

؎0.6V

Figure 3c. Offset Trim Positive Input (10 V FS)

؎0.6V

ROFF

5.6M⍀

10k⍀

AD654

8.25k⍀ 5k⍀

VIN

Figure 3d. Offset Trim Negative Input (–10 V FS)

R1

10k⍀

+5V

+

AD589

–

R2

10k⍀

–5V

R3

10k⍀

R4

10k⍀

R5

100k⍀

؎0.6V

Figure 3e. Offset Trim Bias Network

FULL-SCALE CALIBRATION

Full-scale trim is the calibration of the circuit to produce the

desired output frequency with a full-scale input applied. In most

cases this is accomplished by adjusting the scaling resistor RT.

Precise calibration of the AD654 requires the use of an accurate

voltage standard set to the desired FS value and an accurate

frequency meter. A scope is handy for monitoring output wave-

shape. Verification of converter linearity requires the use of a

switchable voltage source or DAC having a linearity error below

± 0.005%, and the use of long measurement intervals to mini-

mize count uncertainties. Since each AD654 is factory tested for

linearity, it is unnecessary for the end-user to perform this tedious

and time consuming test on a routine basis.

Sufficient FS calibration trim range must be provided to accom-

modate the worst-case sum of all major scaling errors. This

includes the AD654’s 10% full-scale error, the tolerance of the

fixed scaling resistor, and the tolerance of the timing capacitor.

Therefore, with a resistor tolerance of 1% and a capacitor tolerance

of 5%, the fixed part of the scaling resistor should be a maximum

of 84% of nominal, with the variable portion selected to allow

116% of the nominal.

If the input is in the form of a negative current source, the scaling

resistor is no longer required, eliminating the capability of trim-

ming FS frequency in this fashion. Since it is usually not practical

to smoothly vary the capacitance for trimming purposes, an

alternative scheme such as the one shown in Figure 4 is needed.

Designed for a FS of 1 mA, this circuit divides the input into two

R2

100⍀

R4

392⍀

R3

IS

1k⍀

R1

100⍀

AD654

1mA

FS

–V

IR

*

ROFF

100k⍀

f = IS

(20V) CT

؎0.6V

*OPTIONAL

OFFSET TRIM

Figure 4. Current Source FS Trim

and flowing into Pin 3; it constitutes the signal current IT to be

converted. The second path, through another 100 Ω resistor R2,

carries the same nominal current. Two equal valued resistors

offer the best overall stability, and should be either 1% discrete

film units, or a pair from a common array.

Since the 1 mA FS input current is divided into two 500 µA legs

(one to ground and one to Pin 3), the total input signal current

(IS) is divided by a factor of two in this network. To achieve the

same conversion scale factor, CT must be reduced by a factor of

two. This results in a transfer unique to this hookup:

f=

IS

(20 V ) CT

For calibration purposes, resistors R3 and R4 are added to the

network, allowing a ± 15% trim of scale factor with the values

shown. By varying R4’s value the trim range can be modified to

accommodate wider tolerance components or perhaps the cali-

bration tolerance on a current output transducer such as the

AD592 temperature sensor. Although the values of R1–R4 shown

are valid for 1 mA FS signals only, they can be scaled upward

proportionately for lower FS currents. For instance, they should

be increased by a factor of ten for a FS current of 100 µA.

In addition to the offsets generated by the input amplifier’s bias

and offset currents, an offset voltage induced parasitic current

arises from the current fork input network. These effects are

minimized by using the bias current compensation resistor ROFF

and offset trim scheme shown in Figure 3e.

Although device warm-up drifts are small, it is good practice to

allow the devices operating environment to stabilize before trim,

REV. C

–5–

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