AD640(RevD) Просмотр технического описания (PDF) - Analog Devices
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AD640 Datasheet PDF : 19 Pages
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AD640
AC SPECIFICATIONS (VS = ؎5 V, TA = +25؇C, unless otherwise noted)
Model
Parameter
Conditions
AD640J
Min Typ Max
AD640B
Min Typ Max
AD640T
Min Typ Max
Units
SIGNAL INPUTS (Pins 1, 20)
Input Capacitance
Either Pin to COM
2
2
Noise Spectral Density
1 kHz to 10 MHz
2
2
Tangential Sensitivity
BW = 100 MHz
–72
–72
2
pF
2
nV/√Hz
–72
dBm
3 dB BANDWIDTH
Each Stage
All Five Stages
LOGARITHMIC OUTPUTS5
Slope Current, IY
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
Intercept, Dual AD640s10, 11
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
350
350
Pins 1 & 20 to 10 & 11
145
145
350
MHz
145
MHz
0.96 1.0 1.04 0.98 1.0
1.02
0.88 0.94 1.00 0.91 0.94 0.97
0.82 0.90 0.98 0.86 0.90 0.94
0.88
0.88
0.85
0.85
–90.6
–88.6
–87.6
–86.3
–83.9
–80.3
–86.6
–90.0
–88.6
–87.6
–86.3
–83.9
–80.3
–87.6
0.98
0.91
0.86
–90.0
1.0 1.02
0.94 0.97
0.90 0.94
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
–87.6
mA
mA
mA
mA
mA
dBm
dBm
dBm
dBm
dBm
AC LINEARITY
–40 dBm to –2 dBm12
–35 dBm to –10 dBm12
–75 dBm to 0 dBm10
–70 dBm to –10 dBm10
–75 dBm to +15 dBm13
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 10 kHz
0.5 2.0
0.25 1.0
0.75 3.0
0.5 2.0
0.5 3.0
0.5
1.0
0.25 0.5
0.75 1.5
0.5
1.0
0.5
1.5
0.5 1.0
dB
0.25 0.5
dB
0.75 1.5
dB
0.5 1.0
dB
0.5 1.5
dB
PACKAGE OPTION
20-Lead Ceramic SBDIP Package (D)
20-Terminal Ceramic LCC (E)
20-Lead Plastic DIP Package (N)
20-Lead Plastic Leaded Chip Carrier (P)
AD640]N
AD640JP
AD640BE
AD640BP
AD640TD
AD640TE
NUMBER OF TRANSISTORS
155
155
155
NOTES
1Logarithms to base 10 are used throughout. The response is independent of the sign of V IN.
2Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/ °C.
3Overall gain is trimmed using a ± 200 µV square wave at 2 kHz, corrected for the onset of compression.
4The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
5Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured
by linear regression over central region of transfer function.
6The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG 10 (VX/1 V).
7The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
8Operating in circuit of Figure 24 using ± 0.1% accurate values for RLA and RLB. Includes slope and nonlinearity errors. Input offset errors also included for
VIN >3 mV dc, and over the full input range in ac applications.
9Essentially independent of supply voltages.
10Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms.
11For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
for dual AD640 system.
12Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms.
13Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate
outgoing quality levels.
Specifications subject to change without notice.
THERMAL CHARACTERISTICS
20-Lead Ceramic SBDIP Package (D-20)
20-Terminal Ceramic LCC (E-20-1)
20-Lead Plastic DIP Package (N-20)
20-Lead Plastic Leaded Chip Carrier (P-20)
JC (؇C/W)
25
25
24
28
JA (؇C/W)
85
85
61
75
REV. D
–3–
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