AD603(RevC) Просмотр технического описания (PDF) - Analog Devices

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AD603
(Rev.:RevC)

Low Noise, 90 MHz Variable-Gain Amplifier

Analog Devices 

AD603

3.0

2.5

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

VC

1.0 1.1

Figure 13. Gain Error for Cascaded Stages–Low Ripple

Mode

90

85

80

75

70

65

60

55

50

–0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

VC

Figure 14. ISNR vs. Control Voltage–Low Ripple Mode

THEORY OF THE AD603

A Low Noise AGC Amplifier

Figure 15 shows the ease with which the AD603 can be connected

as an AGC amplifier. The circuit illustrates many of the points

previously discussed: It uses few parts, has linear-in-dB gain,

operates from a single supply, uses two cascaded amplifiers in

sequential gain mode for maximum S/N ratio, and an external

resistor programs each amplifier’s gain. It also uses a simple

temperature-compensated detector.

The circuit operates from a single 10 V supply. Resistors R1,

R2, R3, and R4 bias the common pins of A1 and A2 at 5 V.

This pin is a low impedance point and must have a low impedance

path to ground, here provided by the 100 µF tantalum capacitors

and the 0.1 µF ceramic capacitors.

The cascaded amplifiers operate in sequential gain. Here, the

offset voltage between the pins 2 (GNEG) of A1 and A2 is

1.05 V (42.14 dB × 25 mV/dB), provided by a voltage divider

consisting of resistors R5, R6, and R7. Using standard values,

the offset is not exact, but it is not critical for this application.

The gain of both A1 and A2 is programmed by resistors R13

and R14, respectively, to be about 42 dB; thus the maximum

gain of the circuit is twice that, or 84 dB. The gain-control

range can be shifted up by as much as 20 dB by appropriate

choices of R13 and R14.

The circuit operates as follows. A1 and A2 are cascaded.

Capacitor C1 and the 100 Ω of resistance at the input of A1

form a time-constant of 10 µs. C2 blocks the small dc offset

voltage at the output of A1 (which might otherwise saturate A2

at its maximum gain) and introduces a high-pass corner at about

16 kHz, eliminating low frequency noise.

A half-wave detector is used, based on Q1 and R8. The current

into capacitor CAV is just the difference between the collector

current of Q2 (biased to be 300 µA at 300 K, 27°C) and the col-

lector current of Q1, which increases with the amplitude of the

10V

THIS CAPACITOR SETS

AGC TIME CONSTANT

R9

1.54k⍀

C7

0.1␮F 10V

VAGC

Q2

2N3906

C8

0.1␮F 10V

CAV

C1

R13

0.1␮F

Q1

0.1␮F

2.49k⍀

2N3904

J1

A1

RT

100⍀1

10V

AD603

C2

0.1␮F

R14

2.49k⍀

A2

R8

806⍀

R1

10V

AD603

2.49k⍀

R3

+C3

C4

R2

2.49k⍀

100␮F2 0.1␮F 2.49k⍀

+C5

C6

R4

100␮F2 0.1␮F 2.49k⍀

AGC LINE

R5

5.49k⍀

5.5V

NOTES

1RT PROVIDES A 50⍀ INPUT IMPEDANCE

2C3 AND C5 ARE TANTALUM

1V OFFSET FOR

SEQUENTIAL GAIN

R6

1.05k⍀

R7

3.48k⍀

10V

6.5V

Figure 15. A Low Noise AGC Amplifier

R10

1.24k⍀

C11

0.1␮F

R11

3.83k⍀

5V

R12

4.99k⍀

C9

0.1␮F

J2

C10

0.1␮F

REV. C

–9–

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