EVAL-AD5790SDZ Просмотр технического описания (PDF) - Analog Devices

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EVAL-AD5790SDZ

System Ready, 20-Bit, ±2 LSB INL, Voltage Output DAC

Analog Devices 

AD5790

Data Sheet

Parameter

Output Enabled Glitch Impulse

Digital Feedthrough

DC Output Impedance (Normal Mode)

DC Output Impedance (Output

Clamped to Ground)

REFERENCE INPUTS

VREFP Input Range

VREFN Input Range

Input Bias Current

Input Capacitance

LOGIC INPUTS

Input Current5

Input Low Voltage, VIL

Input High Voltage, VIH

Pin Capacitance

LOGIC OUTPUT (SDO)

Output Low Voltage, VOL

Output High Voltage, VOH

High Impedance Leakage Current

High Impedance Output Capacitance

POWER REQUIREMENTS

VDD

VSS

VCC

IOVCC

IDD

ISS

ICC

IOICC

DC Power Supply Rejection Ratio

AC Power Supply Rejection Ratio

B Version1

Min

Typ

Max

57

0.27

3.4

6

Unit

nV-sec

nV-sec

kΩ

kΩ

5

VSS + 2.5

−20

−4

−0.63

−0.63

1

−1

0.7 × IOVCC

5

IOVCC − 0.5

3

7.5

VDD − 33

2.7

1.71

10.3

−10

600

52

±7.5

±1.5

90

90

VDD − 2.5

V

0

V

+20

nA

+4

pF

+1

µA

0.3 × IOVCC V

V

pF

0.4

V

V

±1

µA

pF

VSS + 33

−2.5

5.5

5.5

14

−14

900

140

V

V

V

V

mA

mA

µA

µA

µV/V

µV/V

dB

dB

Test Conditions/Comments

On removal of output ground clamp

TA = 0°C to 105°C

VREFP, VREFN

IOVCC = 1.71 V to 5.5 V

IOVCC = 1.71 V to 5.5 V

IOVCC = 1.71 V to 5.5 V, sinking 1 mA

IOVCC = 1.71 V to 5.5 V, sourcing 1 mA

All digital inputs at DGND or IOVCC

IOVCC ≤ VCC

SDO disabled

∆VDD ± 10%, VSS = −15 V

∆VSS ± 10%, VDD = 15 V

∆VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V

∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V

1 Temperature range: −40°C to +125°C, typical conditions: TA = +25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.

2 Performance characterized with the AD8675ARZ output buffer.

3 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.

4 The AD5790 is configured in unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead

capacitance, and so forth).

5 Current flowing in an individual logic pin.

Rev. E | Page 4 of 27

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