EVAL-AD5781SDZ(RevD) Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD5781SDZ Datasheet PDF : 28 Pages
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AD5781
PIN CONFIGURATION AND FUNCTION DESCRIPTION
Data Sheet
INV 1
VOUT 2
VREFPS 3
VREFPF 4
VDD 5
RESET 6
20 RFB
19 AGND
AD5781 18 VSS
TOP VIEW 17 VREFNS
(Not to Scale) 16 VREFNF
15 DGND
CLR 7
14 SYNC
LDAC 8
13 SCLK
VCC 9
IOVCC 10
12 SDIN
11 SDO
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
INV
Connection to Inverting Input of External Amplifier. See the AD5781 Features section for further details.
2
VOUT
Analog Output Voltage.
3
VREFPS
Positive Reference Sense Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the VREFPF pin. See the AD5781 Features section for further details.
4
VREFPF
Positive Reference Force Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the VREFPS pin. See AD5781 Features section for further details.
5
VDD
Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected. VDD should be decoupled to
AGND.
6
RESET
Active Low Reset Logic Input Pin. Asserting this pin returns the AD5781 to its power-on status.
7
CLR
Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and
updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos
complement.
8
LDAC
Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog output.
When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write
cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin
should not be left unconnected.
9
VCC
Digital Supply Connection. A voltage in the range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND.
10
IOVCC
11
SDO
Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of
1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC.
Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input.
12
SDIN
Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
13
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at clock rates of up to 35 MHz.
14
SYNC
Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. When
SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks.
The input shift register is updated on the rising edge of SYNC.
15
DGND
Ground Reference Pin for Digital Circuitry.
16
VREFNF
17
VREFNS
Negative Reference Force Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the VREFNS pin. See the AD5781 Features section for further details.
Negative Reference Sense Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the VREFNF pin. See the AD5781 Features section for further details.
18
VSS
Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. VSS should be decoupled to
AGND.
19
AGND
Ground Reference Pin for Analog Circuitry.
20
RFB
Feedback Connection for External Amplifier. See the AD5781 Features section for further details.
Rev. D | Page 8 of 28
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