EVAL-AD5780SDZ(RevC) Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD5780SDZ Datasheet PDF : 28 Pages
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AD5780
Data Sheet
Parameter
REFERENCE INPUTS
VREFP Input Range
VREFN Input Range
Input Bias Current
Input Capacitance
LOGIC INPUTS
Input Current5
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
LOGIC OUTPUT (SDO)
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
VDD
VSS
VCC
IOVCC
IDD
ISS
ICC
IOICC
DC Power Supply Rejection Ratio
AC Power Supply Rejection Ratio
A, B Versions1
Min
Typ
Max
5
VSS + 2.5
−20
−4
−0.63
−0.63
1
VDD − 2.5
0
+20
+4
−1
0.7 × IOVCC
5
+1
0.3 × IOVCC
0.4
IOVCC − 0.5
±1
3
7.5
VSS + 33
VDD − 33
−2.5
2.7
5.5
1.71
5.5
10.3
14
−10
−14
600
900
52
140
±7.5
±1.5
90
90
Unit
V
V
nA
pF
μA
V
V
pF
V
V
μA
pF
V
V
V
V
mA
mA
μA
μA
μV/V
μV/V
dB
dB
Test Conditions/Comments
TA = 0°C to 105°C
VREFP, VREFN
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
All digital inputs at DGND or IOVCC
IOVCC ≤ VCC
SDO disabled
∆VDD ± 10%, VSS = −15 V
∆VSS ± 10%, VDD = 15 V
∆VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V
∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with the AD8675ARZ output buffer.
3 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
4 The AD5780 is configured in the unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead
capacitance, and so forth).
5 Current flowing in an individual logic pin.
Rev. C | Page 4 of 28
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