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AD5801

Piezo-Electric Actuator Controller

Analog Devices 

AD5801

Preliminary Technical Data

General Description

The AD5801 is a high efficiency ultrasonic motor controller

with two Class D-type output drivers. These Class D-type

drivers can be used independently or configured as an H-bridge

driver, and have full pattern programmability. There are also six

integrated drivers which can be operated independently and

have programmable output patterns. The AD5801 also has

integrated drivers which are programmable from 60mA to

200mA, and may be used for a combination of Shutter and

NDF/IRIS control.

The operation modes of the drivers are invoked by the AD5801

using an I2C compatible interface.

Driver Stage for Auto Focus

Channel FA sad FB are Class D-type outputs with an on-

resistance, Ron, of 0.5Ω maximum over temperature. These

outputs have been integrated to eliminate the need to use

external FET drivers for the Auto Focus function and can be

configured as a PWM source.

The driving frequency of outputs FA and FB is configured in

the Registers PWUNIT and PWMPERIOD. The PWUNIT

defines the basic time interval from when the counters can

PWMPERIOD

derive a count, and is used to set the divide factor used to divide

the clock frequency of the master clock derived from the

integrated PLL in the AD5801, or the clock applied to EXTCLK.

The effective phase difference in the outputs FA and FB can be

programmed in the PWMAFATx and PWMAFBTx registers,

and the waveforms can be programmed with varying or

constant duty cycles (See Figure 3).

The PWM patterns from Channels FA and FA are enabled in

the PWMENABLE and PWMPOLARITY Registers. The

PWMENABLE register allows the user to enable the drivers

channels required, the PWMPOLARITY Register is used to set

the polarity of the drive patterns when they are initiated. When

the outputs are disabled they can be set configured in a High

Impedance, or High or Low state.

To move the motor in reverse the user has the choice of either

setting new values to the PWMAFATx and PWMAFBTx

registers or setting a direction bit in the ACTIVE Register

which interchanges the timing values between the driver

outputs FA and FB. The actual duration of the drive operation is

defined in the AFSTEPS Register, this allows the user to enter

the number of PWMPERIODS required for one move of the

lens.

PWM

FA

PWM

FB

PWMAFAT1

PWMAFAT2

PWMAFBT1

PWMAFBT2

Figure 3. Timing Diagram for Class D-type Driver FA and FB.

Driver Stages FC – ZD

Drivers FC, FD, and ZA – ZD are independent driver channels

capable of driving 8mA. These channels can be configured as

PWM drivers and used to drive external FETs or Bridges for

Zoom control, or for other timing functions.

As with Drivers FA and FB the driving frequency is

programmed in the PWMUNIT and PWMPERIOD Registers,

and the programmed PWM patterns are enabled by the

PWMENABLE and PWMPOLARITY Registers. These driver

outputs have four registers (PWMAFCTx, PWMAFDTx,

PWMAZATx – PWMAZDTx ) which allow the user to

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