AD5687R(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD5687R Datasheet PDF : 28 Pages
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Data Sheet
AD5689R/AD5687R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
Min
STATIC PERFORMANCE2
AD5689R
Resolution
16
Relative Accuracy
Differential
Nonlinearity
AD5687R
Resolution
12
Relative Accuracy
Differential
Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
Offset Error Drift3
Gain Temperature
Coefficient3
DC Power Supply
Rejection Ratio3
DC Crosstalk3
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
0
Capacitive Load Stability
Resistive Load4
1
Load Regulation
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
A Grade1
Typ Max
Min
16
±2 ±8
±2 ±8
±1
12
±0.12 ±2
±1
0.4
+0.1
+0.01
±0.02
±0.01
±1
±1
4
±4
±0.2
±0.2
±0.25
±0.25
0.15
±2
±3
±2
VREF
0
2 × VREF
0
2
10
1
80
80
40
25
2.5
B Grade1
Typ Max
Unit
Test Conditions/Comments
±1 ±2
±1 ±3
±1
Bits
LSB
Gain = 2
Gain = 1
LSB
Guaranteed monotonic by design
±0.12 ±1
±1
0.4 1.5
+0.1 ±1.5
+0.01 ±0.1
±0.02 ±0.1
±0.01 ±0.1
±0.2
±1
±1
0.15
±2
±3
±2
VREF
2 × VREF
2
10
80
80
40
25
2.5
Bits
LSB
LSB
Guaranteed monotonic by design
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
ppm
All 0s loaded to DAC register
All 1s loaded to DAC register
External reference; gain = 2; TSSOP
Internal reference; gain = 1; TSSOP
Of FSR/°C
mV/V
DAC code = midscale;
VDD = 5 V ± 10%
µV
µV/mA
µV
Due to single channel, full-scale
output change
Due to load current change
Due to powering down
(per channel)
V
V
nF
nF
kΩ
µV/mA
µV/mA
mA
Ω
µs
Gain = 1
Gain = 2, see Figure 32
RL = ∞
RL = 1 kΩ
5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
See Figure 32
Coming out of power-down
mode; VDD = 5 V
Rev. 0 | Page 3 of 28
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