AD5684R Просмотр технического описания (PDF) - Analog Devices
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AD5684R Datasheet PDF : 32 Pages
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Data Sheet
AD5686R/AD5685R/AD5684R
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =
2.7 V to 5.5 V.
Table 5.
Parameter1
Symbol
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
Unit
SCLK Cycle Time
t1
66
40
ns
SCLK High Time
t2
33
20
ns
SCLK Low Time
t3
33
20
ns
SYNC to SCLK Falling Edge
t4
33
20
ns
Data Setup Time
t5
5
5
ns
Data Hold Time
t6
5
5
ns
SCLK Falling Edge to SYNC Rising Edge
t7
15
10
ns
Minimum SYNC High Time
t8
60
30
ns
Minimum SYNC High Time
t9
60
30
ns
SDO Data Valid from SCLK Rising Edge
t10
36
25
ns
SCLK Falling Edge to SYNC Rising Edge
t115
15
10
ns
SYNC Rising Edge to SCLK Rising Edge
t125
15
10
ns
1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA IOL
SCLK
SYNC
SDIN
SDO
TO OUTPUT
PIN CL
20pF
VOH (MIN)
200µA IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
t8
t4
t5
DB23
24
t6
DB0 DB23
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
t10
DB23
UNDEFINED
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
48
t11
t12
DB0
DB0
Rev. 0 | Page 7 of 32
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