AD5684R Просмотр технического описания (PDF) - Analog Devices
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AD5684R Datasheet PDF : 32 Pages
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AD5686R/AD5685R/AD5684R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single, Combined or All Channel Update)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time2
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
33
16
16
15
5
5
15
20
16
25
30
20
30
30
4.5
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
20
10
10
10
5
5
10
20
10
15
20
20
30
30
4.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
2 Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
SCLK
SYNC
SDIN
LDAC1
t9
t8
t4
DB23
t6
t5
LDAC2
RESET
t13
VOUT
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t3
t2
t7
DB0
t12
t10
t11
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 32
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