AD5620 Просмотр технического описания (PDF) - Analog Devices

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AD5620

Single, 12-/14-/16-Bit nanoDAC with 5 ppm/°C On-Chip Reference in SOT-23

Analog Devices 

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AD5620/AD5640/AD5660

VDD 1 AD5620/ 8 GND

VREFOUT 2 AD5640/ 7 DIN

AD5660

VFB 3 TOP VIEW 6 SCLK

(Not to Scale)

VOUT 4

5 SYNC

Figure 3. SOT-23 Pin Configuration

VDD 1

VREFOUT 2

VFB 3

VOUT 4

AD5620/

AD5640/

AD5660

TOP VIEW

(Not to Scale)

8 GND

7 DIN

6 SCLK

5 SYNC

Figure 4. MSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1

VDD

Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND.

2

VREFOUT

Reference Voltage Output.

3

VFB

Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation.

4

VOUT

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

5

SYNC

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When

SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following

clocks. The DAC is updated following the 24th clock cycle for the AD5660 and the 16th clock cycle for

AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an

interrupt, and the write sequence is ignored by the DAC.

6

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at rates up to 30 MHz.

7

DIN

Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register.

Data is clocked into the register on the falling edge of the serial clock input.

8

GND

Ground Reference Point for all Circuitry on the Part.

Rev. F | Page 9 of 28

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