AD5535(RevPrE) Просмотр технического описания (PDF) - Analog Devices

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AD5535
(Rev.:RevPrE)

32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V

Analog Devices 

AD5535

Preliminary Technical Data

Table 5. Pin Function Descriptions

Pin

Function

AGND

Analog GND Pins.

AVCC

Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.

VPP

Output Amplifier High Voltage Supply. Voltage range from (REF_IN × 50) + 10 V to 225 V.

V+

V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V.

V–

V– Amplifier Supply Pins. Voltage range from −4.75 V to −5.25 V.

PGND

Output Amplifier Ground Reference Pins.

DGND

Digital GND Pins.

DVCC

Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.

DAC_GND

Reference GND Supply for All the DACs.

REF_IN

Reference Voltage for Channels 0–31. Reference input range is 1 V to 4 V and can be used to program the full-scale

output voltage from 50 V to 200 V.

VOUT (0–31)

Analog Output Voltages from the 32 Channels.

ANODE

Anode of Internal Diode for Diode Temperature Measurement.

CATHODE

Cathode of Internal Diode for Diode Temperature Measurement.

SYNC

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in

on the falling edge of SCLK.

SCLK1

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds of up to

30 MHz.

DIN1

Serial Data Input. Data must be valid on the falling edge of SCLK.

TEST

Allows the same data to be simultaneously loaded to all channels of the AD5535. This pin is used for calibration purposes

when loading zero scale and full scale to all channels. To invoke this feature, take the TEST pin high. In normal operation,

TEST should be tied low.

RESET1

Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is

loaded to the DACs.

1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.

Rev. PrE | Page 8 of 16

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