AD5444 Просмотр технического описания (PDF) - Analog Devices
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AD5444 Datasheet PDF : 28 Pages
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AD5444/AD5446
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1 1
10 RFB
IOUT2 2
AD5444/
AD5446
9 VREF
GND 3
8 VDD
TOP VIEW
SCLK 4 (Not to Scale) 7 SDO
SDIN 5
6 SYNC
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
IOUT1
2
IOUT2
3
GND
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.
By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to the rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low,
data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising
edge of SYNC.
7
SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to data loaded to the shift register.
8
VDD
9
VREF
10
RFB
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input.
DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.
Rev. C | Page 7 of 28
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