AD5444 Просмотр технического описания (PDF) - Analog Devices
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AD5444 Datasheet PDF : 28 Pages
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AD5444/AD5446
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
Update Rate
VDD = 4.5 V to
5.5 V
50
20
8
8
8
5
4.5
5
30
23
2.7
VDD = 2.5 V to
5.5 V
50
20
8
8
8
5
4.5
5
30
30
2.7
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Conditions/Comments
Maximum clock frequency.
SCLK cycle time.
SCLK high time.
SCLK low time.
SYNC falling edge to SCLK active edge setup time.
Data setup time.
Data hold time.
SYNC rising edge to SCLK active edge setup time
Minimum SYNC high time.
SCLK active edge to SDO valid.
Consists of cycle time, SYNC high time, data setup time and output
voltage settling time.
1 Guaranteed by design and characterization; not subject to production test.
t1
SCLK
t4
SYNC
t2
t3
t7
t8
t6
t5
SDIN
DB15
DB0
Figure 2. Standalone Timing Diagram
SCLK
SYNC
SDIN
t4
t6
t5
DB15 (N)
t1
t2
t3
DB0 (N)
t9
DB15
(N + 1)
SDO
DB15 (N)
NOTES
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain Timing Diagram
t7
t8
DB0
(N + 1)
DB0 (N)
Rev. C | Page 5 of 28
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