AD532J Просмотр технического описания (PDF) - Analog Devices

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AD532J

Internally Trimmed Integrated Circuit Multiplier

Analog Devices 

AD532

FUNCTIONAL DESCRIPTION

The functional block diagram for the AD532 is shown in

Figure 1and the complete schematic in Figure 14. In the

multiplying and squaring modes, Z is connected to the output

to close the feedback around the output op amp. In the divide

mode, it is used as an input terminal.

The X and Y inputs are fed to high impedance differential

amplifiers featuring low distortion and good common-mode

rejection. The amplifier voltage offsets are actively laser trimmed to

zero during production. The product of the two inputs is resolved

in the multiplier cell using Gilbert’s linearized transconductance

technique. The cell is laser trimmed to obtain VOUT = (X1 −

X2)(Y1 − Y2)/10 volts. The built-in op amp is used to obtain low

output impedance and make possible self-contained operation.

The residual output voltage offset can be zeroed at VOS in critical

applications. Otherwise, the VOS pin should be grounded.

X2

Y1

X1

COM

Y2

R2

R6

R8

R16

R23

Q1

Q2

R34

R9

R1

Q3 Q4

R3

Q7 Q8 Q14 Q15

Q9

Q10

R13

Q16 Q17

R20

R22

R21

R10

Q5 Q6

Q11

Q12

R19

R32

R11

R4 R5

R14

Q28

Q13

R12 R15

R18

Q18

Q20

Q19

R24 R25

R27

C1

Q21

Q25

+VS

Z

R33

R30

R31

Q22 Q26

R28

Q23

R29

VOS

OUTPUT

Q24

Q27

R26

–VS CAN

Figure 14. Schematic Diagram

Rev. D | Page 10 of 16

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