AD5317BRU-REEL Просмотр технического описания (PDF) - Analog Devices

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AD5317BRU-REEL

2.5 V to 5.5 V, 400
A, Quad Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

Analog Devices 

PIN CONFIGURATION

CLR 1

16 SDO

LDAC 2 AD5307/ 15 SYNC

VDD 3

AD5317/ 14 SCLK

AD5327

VOUTA 4

13 DIN

TOP VIEW

VOUTB 5 (Not to Scale) 12 GND

VOUTC 6

11 VOUTD

VREFAB 7

10 PD

VREFCD 8

9 DCEN

AD5307/AD5317/AD5327

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Mnemonic

CLR

LDAC

VDD

VOUTA

VOUTB

VOUTC

VREFAB

VREFCD

DCEN

PD

VOUTD

GND

DIN

SCLK

SYNC

SDO

PIN FUNCTION DESCRIPTIONS

Function

Active Low Control Input that Loads All Zeros to All Input and DAC Registers. Therefore, the outputs

also go to 0 V.

Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC

Registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have

new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied

permanently low.

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled

with a 10 mF capacitor in parallel with a 0.1 mF capacitor to GND.

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Reference Input Pin for DACs A and B. It may be configured as a buffered or an unbuffered input to each or

both of the DACs, depending on the state of the BUF bits in the serial input words to DACs A and B. It

has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.

Reference Input Pin for DACs C and D. It may be configured as a buffered or an unbuffered input to each or

both of the DACs, depending on the state of the BUF bits in the serial input words to DACs C and D. It

has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.

This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a

daisy chain. The pin should be tied low if it is being used in standalone mode.

Active low control input that acts as a hardware power-down option. All DACs go into power-down

mode when this pin is tied low. The DAC outputs go into a high impedance state and the current con-

sumption of the part drops to 300 nA @ 5 V (90 nA @ 3 V).

Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after

each write cycle.

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in

on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the

rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading

back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge

of SCLK and is valid on the falling edge of the clock.

REV. A

–7–

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